Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 Design-In Page 128 of 182
2.2.2 Footprint and paste mask
The following figure describes the footprint and provides recommendations for the paste mask for
LISA-U2 modules. These are recommendations only and not specifications. Note that the copper and
solder masks have the same size and position.
33.2 mm [1307.1 mil]
22.4 mm [881.9 mil]
2.3 mm
[90.6 mil]
0.8 mm
[31.5 mil]
1.1 mm
[43.3 mil]
0.8 mm
[31.5 mil]
1.0 mm
[39.3 mil]
5.7 mm
[224.4 mil]
33.2 mm [1307.1 mil]
22.4 mm [881.9 mil]
2.3 mm
[90.6 mil]
1.2 mm
[47.2 mil]
1.1 mm
[43.3 mil]
0.8 mm
[31.5 mil]
0.9 mm
[35.4 mil]
5.7 mm
[224.4 mil]
0.6 mm
[23.6 mil]
Stencil: 150 µm
Figure 61: LISA-U2 modules suggested footprint and paste mask
To improve the wetting of the half vias, reduce the amount of solder paste under the module and
increase the volume outside of the module by defining the dimensions of the paste mask to form a T-
shape (or equivalent) extending beyond the copper mask. The solder paste should have a total
thickness of 150 µ m.
☞ The paste mask outline needs to be considered when defining the minimal distance to the next
component.
☞ The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to
the specific production processes (e.g. soldering etc.) of the customer.
The implemetation of a step stencil (a stencil with different material thicknesses) should be
considered if very different sized components must be soldered on the same application PCB: while
high density chip housings with small pitch need small solder paste quantities for the avoidance of
short-circuits and therefore require thin stencils, large components need more solder paste for a safe
connection and thus thicker stencils.
The bottom layer of LISA-U2 series modules has two unprotected copper areas for GND, shown in
Figure 62.
☞ Consider “No-routing” areas for the LISA-U2 modules footprint as follows: signal keep-out area on
the top layer of the application board, below LISA-U2 modules, due to GND opening on module
bottom layer (see Figure 62).