Integration Manual
Table Of Contents
- Document Information
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.9.1 Serial interfaces configuration
- 1.9.2 Asynchronous serial interface (UART)
- 1.9.2.1 UART features
- 1.9.2.2 UART signal behavior
- 1.9.2.3 UART and power-saving
- 1.9.2.4 UART application circuits
- Providing the full RS-232 functionality (using the complete V.24 link)
- Providing the TxD, RxD, RTS, CTS and DTR lines only (not using the complete V.24 link)
- Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
- Providing the TxD and RxD lines only (not using the complete V24 link)
- Additional considerations
- 1.9.3 USB interface
- 1.9.4 SPI interface
- 1.9.5 MUX protocol (3GPP TS 27.010)
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U2 module integration
- 1.15 Approvals
- 1.15.1 European Conformance CE mark
- 1.15.2 US Federal Communications Commission notice
- 1.15.3 Innovation, Science, Economic Development Canada notice
- 1.15.4 Australian Regulatory Compliance Mark
- 1.15.5 ICASA Certification
- 1.15.6 KCC Certification
- 1.15.7 ANATEL Certification
- 1.15.8 CCC Certification
- 1.15.9 Giteki Certification
- 2 Design-In
- 3 Features description
- 3.1 Network indication
- 3.2 Antenna detection
- 3.3 Jamming Detection
- 3.4 TCP/IP and UDP/IP
- 3.5 FTP
- 3.6 HTTP
- 3.7 SSL/TLS
- 3.8 Dual stack IPv4/IPv6
- 3.9 AssistNow clients and GNSS integration
- 3.10 Hybrid positioning and CellLocate®
- 3.11 Control Plane Aiding / Location Services (LCS)
- 3.12 Firmware update Over AT (FOAT)
- 3.13 Firmware update Over the Air (FOTA)
- 3.14 In-Band modem (eCall / ERA-GLONASS)
- 3.15 SIM Access Profile (SAP)
- 3.16 Smart Temperature Management
- 3.17 Bearer Independent Protocol
- 3.18 Multi-Level Precedence and Pre-emption Service
- 3.19 Network Friendly Mode
- 3.20 Power saving
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration from LISA-U1 to LISA-U2 series
- A.1 Checklist for migration
- A.2 Software migration
- A.2.1 Software migration from LISA-U1 series to LISA-U2 series modules
- A.3 Hardware migration
- A.3.1 Hardware migration from LISA-U1 series to LISA-U2 series modules
- A.3.2 Pin-out comparison LISA-U1 series vs. LISA-U2 series
- A.3.3 Layout comparison LISA-U1 series vs. LISA-U2 series
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 36 of 182
1.5.5 Interface supply (V_INT)
The same voltage domain used internally to supply the digital interfaces is also available on the V_INT
pin. The internal regulator that generates the V_INT supply is a switching step down converter that is
directly supplied from VCC. The voltage regulator output is set to 1.8 V (typical) when the module is
switched on and is disabled when the module is switched off or when the RESET_N pin is forced the
low level. The switching regulator operates in Pulse Width Modulation (PWM) for high output current
mode but automatically switches to Pulse Frequency Modulation (PFM) at low output loads for
greater efficiency, e.g. when the module is in idle mode between paging periods.
V_INT supply output pin provides internal short circuit protection to limit start-up current and protect
the device in short circuit situations. No additional external short circuit protection is required.
Name
Description
Remarks
V_INT
Digital Interfaces supply output
V_INT = 1.8V (typical) generated by the module when it
is switched-on and the RESET_N (external reset input
pin) is not forced to the low level.
V_INT is the internal supply for digital interfaces.
The user may draw limited current from this supply rail.
Table 15: Interface supply pin
☞ The V_INT pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection levels could be required if the line is externally accessible on the application
board. Higher protection levels can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) on the line connected to this pin, close to the accessible point.
Since it supplies internal digital circuits (see Figure 3), V_INT is not suited to directly supply any
sensitive analog circuit: the voltage ripple can range from 15 mVpp during active mode (PWM), to
70 mVpp in idle mode (PFM).
☞ V_INT can be used to supply external digital circuits operating at the same voltage level as the
digital interface pins, i.e. 1.8 V (typical). It is not recommended to supply analog circuitry without
adequate filtering for digital noise.
☞ Do not apply loads which might exceed the limit for the maximum available current from the V_INT
supply, as this can cause malfunctions in internal circuitry supplies to the same domain. The
detailed electrical characteristics are described in the LISA-U2 series Data Sheet [1].
☞ V_INT can only be used as an output; do not connect any external regulator on V_INT. If not used,
this pin should be left unconnected.
The V_INT digital interfaces supply output is mainly used to:
Pull-up DDC (I
2
C) interface signals (see section 1.10.2 for more details)
Pull-up SIM detection signal (see section 1.8 for more details)
Supply voltage translators to connect digital interfaces of the module to a 3.0 V device (see
sections 1.9.2.4, 1.9.4.4 for more details)
Supply a 1.8 V u-blox 6 or subsequent GNSS receiver (see section 1.10.2 for more details)
Indicate when the module is switched on and the RESET_N external hardware reset input is not
forced low (see sections 1.6.1.5, 1.6.2 and 1.6.3 for more details)