Integration Manual

LISA-U2 series - System Integration Manual
UBX-13001118 - R25 System description Page 73 of 182
☞ In this case, the first character sent when the module is in idle mode will be a wake-up character
and will not be a valid communication character (see section 1.9.2.3 for the complete description).
☞ If power saving is enabled, the application circuit with the TxD and RxD lines only is not
recommended. During command mode, the DTE must send to the module a wake-up character or
a dummy “AT” before each command line (see section 1.9.2.3 for the complete description), but
during data mode, the wake-up character or the dummy “AT” would affect the data
communications.
Additional considerations
If a 3.0 V application processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to
the corresponding 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost
solution, by means of an appropriate voltage divider. Consider the value of the pull-up integrated at
the input of the module (DCE) for the correct selection of the voltage divider resistance values and
mind that any DTE signal connected to the module must be tri-stated or set low when the module is
in power-down mode and during the module power-on sequence (at least until the activation of the
V_INT supply output of the module), to avoid latch-up of circuits and allow a clean boot of the module
(see the remark below). Moreover, the voltage scaling from any 1.8 V output of the cellular module
(DCE) to the corresponding 3.0 V input of the application processor (DTE) can be implemented by
means of an appropriate low-cost non-inverting buffer with open drain output. The non-inverting
buffer should be supplied by the V_INT supply output of the cellular module. Consider the value of the
pull-up integrated at each input of the DTE (if any) and the baud rate required by the application for
the appropriate selection of the resistance value for the external pull-up biased by the application
processor supply rail.
☞ If the module USB interface is connected to the application processor, it is highly recommended
to provide direct access to the RxD, TxD, CTS and RTS lines of the module for execution of the
firmware upgrade over UART using the u-blox EasyFlash tool and for debugging purposes:
testpoints can be added on the lines to accommodate the access and a 0 Ω series resistor must
be mounted on each line to detach the module pin from any other connected device. Otherwise, if
the USB interface is not connected to the application processor, it is highly recommended to
provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of the firmware
upgrade over USB and for debugging purposes. In both cases, provide as well access to the
RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start
the module firmware upgrade (see the Firmware Update Application Note [16]).
☞ If the UART interface is not used, all the UART interface pins can be left unconnected, but it is
highly recommended to provide direct access to the RxD, TxD, CTS and RTS lines for execution of
the firmware upgrade using the u-blox EasyFlash tool and for debugging purposes .
☞ Any external signal connected to the UART interface must be tri-stated when the module is in
power-down mode, when the external reset is forced low and during the module power-on
sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow a
proper boot of the module. If the external signals connected to the cellular module cannot be tri-
stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159,
or TS5A63157) between the two-circuit connections and set to high impedance during the
module’s power-down mode, when external reset is forced low, and during the power-on sequence.