Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary Design-In
Page 107 of 160
Rank
Function
Pin(s)
Layout
Remarks
1
st
RF Antenna
Main RF input/output
Very Important
Design for 50 characteristic impedance.
See section 2.2.1.1
RF input for Rx diversity
Very Important
Design for 50 characteristic impedance.
See section 2.2.1.1
2
nd
Main DC Supply
Very Important
VCC line should be wide and short. Route away
from sensitive analog signals.
See section 2.2.1.2
3
rd
USB Signals
Very Important
Route USB_D+ and USB_D- as differential lines:
design for 90 differential impedance.
See section 2.2.1.3
4
th
Analog Audio
Careful Layout
Avoid coupling with noisy signals.
See section 2.2.1.4
Audio Inputs
MIC_P, MIC_N
Audio Outputs
SPK_P, SPK_N
5
th
Ground
GND
Careful Layout
Provide proper grounding.
See section 2.2.1.5
6
th
Sensitive Pin:
Careful Layout
Avoid coupling with noisy signals.
See section 2.2.1.6
Backup Voltage
V_BCKP
Power-On
PWR_ON
7
th
High-speed digital pins:
Careful Layout
Avoid coupling with sensitive signals.
See section 2.2.1.7
SPI Signals
SPI_SCLK, SPI_MISO,
SPI_MOSI, SPI_SRDY,
SPI_MRDY
Clock Output
CODEC_CLK
8
th
Digital pins and
supplies:
Common
Practice
Follow common practice rules for digital pin
routing.
See section 2.2.1.8
SIM Card Interface
VSIM, SIM_CLK,
SIM_IO, SIM_RST
Digital Audio
(If implemented)
I2S_CLK, I2S_RXD,
I2S_TXD, I2S_WA
I2S1_CLK, I2S1_RXD,
I2S1_TXD, I2S1_WA
DDC
SCL, SDA
UART
TXD, RXD, CTS, RTS,
DSR, RI, DCD, DTR
External Reset
RESET_N
General Purpose I/O
GPIO1, GPIO2, GPIO3,
GPIO4, GPIO5
GPIO6, GPIO7, GPIO8,
GPIO9, GPIO10, GPIO11,
GPIO12, GPIO13, GPIO14
USB detection
VUSB_DET
Supply for Interfaces
V_INT
Table 44: Pin list in order of decreasing importance for layout design
2.2.1.1 RF antenna connection
The ANT pin (main RF input/output) and the ANT_DIV pin (RF input for diversity receiver provided by LISA-U230
modules) are very critical in layout design. The PCB line must be designed to provide 50 nominal characteristic
impedance and minimum loss up to radiating element.
Provide proper transition between the ANT pad and the ANT_DIV pad to application board PCB
Increase GND keep-out (i.e. clearance) for ANT and ANT_DIV pads to at least 250 µm up to adjacent pads
metal definition and up to 500 µm on the area below the module, as described in Figure 55
USB_D-
USB_D+
VCC
ANT
ANT_DIV