Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary Design-In
Page 129 of 160
External Antenna Enclosure
Application Board
LISA-U200-00
ANT
Radiating
Element
Zo = 50 Ohm
Coaxial Antenna Cable
Antenna Port
Enclosure Port
C
L
Figure 68: LISA-U200-00 antenna port ESD immunity protection application circuit
Reference
Description
Part Number - Manufacturer
C
15 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H150JA01 - Murata
L
39 nH Multilayer Chip Inductor L0G 0402 5%
LQG15HN39NJ102 - Murata
Table 49: Example of components for LISA-U200-00 antenna port ESD immunity protection application circuit
With LISA-U230 modules, the ANT_DIV pin provides ESD immunity up to +4 kV / -4 kV for direct Contact
Discharge and up to +8 kV / -8 kV for Air Discharge: no further precaution to ESD immunity test is needed.
RESET_N pin
The following precautions are suggested for the RESET_N line of LISA-U series modules, depending on the
application board handling, to satisfy ESD immunity test requirements:
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line termination
connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the
application board enclosure
A series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N
pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure
An additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as
possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic
discharge applied to the application board enclosure
It is recommended to keep the connection line to RESET_N as short as possible
Maximum ESD sensitivity rating of the RESET_N pin is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if the RESET_N pin is externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the RESET_N line, close to accessible point
For the RESET_N application circuit description refer to Figure 20 and Table 18 reported in section 1.6.3.