Integration Manual

LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary Design-In
Page 130 of 160
SIM interface
The following precautions are suggested for LISA-U series modules SIM interface (VSIM, SIM_RST, SIM_IO,
SIM_CLK pins), depending on the application board handling, to satisfy ESD immunity test requirements:
 A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to
VSIM, SIM_RST, SIM_IO and SIM_CLK pins to assure SIM interface functionality when an electrostatic
discharge is applied to the application board enclosure
 It is suggested to use as short as possible connection lines at SIM pins
Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if SIM interface pins are externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
 A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or AVX
USB0002) should be mounted on each SIM interface line, close to accessible points (i.e. close to the SIM
card holder)
For the SIM interface application circuit description refer to Figure 21 and Table 21 reported in section 1.8.
Other pins and interfaces
All the module pins that are externally accessible on the device (i.e. the application board where LISA-U series
module is mounted) should be included in the ESD immunity test since they are considered to be a port as
defined in ETSI EN 301 489-1 [11]. Depending on applicability, to satisfy ESD immunity test requirements
according to ESD category level, all the module pins that are externally accessible should be protected up to +4
kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge applied to the enclosure
surface.
The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to
JESD22-A114F). Higher protection level could be required if the relative pin is externally accessible on the
application board. The following precautions are suggested to achieve higher protection level:
 USB interface: a very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics
PESD0402-140 ESD protection device) should be mounted on the USB_D+ and USB_D- lines, close to the
accessible points (i.e. close to the USB connector)
 SPI interface: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L
or AVX USB0002) should be mounted on the SPI_MISO, SPI_MOSI, SPI_SCLK, SPI_MRDY, SPI_SRDY
lines, close to accessible points
 CODEC_CLK: a low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or
AVX USB0001) should be mounted on the CODEC_CLK line, close to accessible point
 Other pins: a general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the relative line, close to accessible point