Integration Manual

Table Of Contents
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 32 of 160
ACTIVE MODE
10-25 mA
10-25 mA
2G case: 0.47-2.12 s
3G case: 0.64-5.12 s
Paging period
Time [s]
Current [mA]
150
100
50
0
Time [ms]
Current [mA]
150
100
50
0
10-25 mA
RX
Enabled
DSP
Enabled
35-40 mA
2G case: 60-130 mA
3G case: 50-90 mA
2G case: 60-130 mA
3G case: 50-90 mA
Figure 15: Description of the VCC current consumption profile versus time when power saving is disabled: the active-mode is
always held, and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception
1.5.4 RTC Supply (V_BCKP)
The V_BCKP pin connects the supply for the Real Time Clock (RTC) and Power-On / Reset internal logic. This
supply domain is internally generated by a linear regulator integrated in the Power Management Unit. The
output of this linear regulator is always enabled when the main voltage supply provided to the module through
VCC is within the valid operating range, with the module switched-off or powered-on.
Name
Description
Remarks
V_BCKP
Real Time Clock supply
V_BCKP output voltage = 2.3 V (typical) on LISA-U1 series
V_BCKP output voltage = 1.8 V (typical) on LISA-U2 series
Generated by the module to supply Real Time Clock when
VCC supply voltage is within valid operating range.
Table 11: Real Time Clock supply pin
The V_BCKP pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin, close to accessible point.