Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 41 of 160
“software” reset, the current parameter settings are saved in the module’s non-volatile memory and a proper
network detach is performed.
When RESET_N is released from the low level, the module automatically starts its power-on sequence from the
reset state. The same procedure is followed for the module reset via AT command after having performed the
network detach and the parameter saving in non-volatile memory.
The internal reset state of all digital pins is reported in the pin description table in LISA-U1 series Data
Sheet [1] and LISA-U2 series Data Sheet [2].
Name
Description
Remarks
RESET_N
External reset input
Internal 10 k pull-up to V_BCKP
Table 17: Reset pin
The RESET_N pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher
protection level could be required if the line is externally accessible on the application board. Higher
protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor
array) on the line connected to this pin, close to accessible point.
For more details about RESET_N circuit precautions for ESD immunity please refer to chapter 2.5.3.
The electrical characteristics of RESET_N are different from the other digital I/O interfaces. The detailed electrical
characteristics are described in LISA-U1 series Data Sheet [1] and LISA-U2 series Data Sheet [2].
RESET_N is pulled high by an integrated 10 k pull-up resistor to V_BCKP. Therefore an external pull-up is not
required on the application board.
Following are some typical examples of application circuits using the RESET_N input pin.
The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground.
If RESET_N is connected to an external device (e.g. an application processor on an application board) an open
drain output can be directly connected without any external pull-up. A push-pull output can be used too: in this
case make sure that the high level voltage of the push-pull circuit is below the maximum voltage operating
range of the RESET_N pin (specified in the RESET_N pin characteristics table in LISA-U1 series Data Sheet [1]
and LISA-U2 series Data Sheet [2]). To avoid unwanted reset of the module make sure to fix the proper level at
the RESET_N input pin in all possible scenarios.
As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) and a series
ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the RESET_N line pin of LISA-U1 series modules
and an additional 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as
possible to the RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic
discharge applied to the application board (for more details, refer to chapter 2.5.3).