Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 42 of 160
LISA-U series
2
V_BCKP
22
RESET_N
Reset
push button
ESD
Open
Drain
Output
Application
Processor
LISA-U series
2
V_BCKP
22
RESET_N
Rint
Rint
FB1
C1
FB2
C3
C2
C4
Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor
Reference
Description
Remarks
ESD
Varistor for ESD protection.
CT0402S14AHSG - EPCOS
C1, C3
47 pF Capacitor Ceramic C0G 0402 5% 50 V
GRM1555C1H470JA01 - Murata
C2, C4
220 nF Capacitor Ceramic X5R 0402 10% 6.3 V
GRM155R60J224KE01 - Murata
FB1, FB2
Chip Ferrite Bead for Noise/EMI Suppression
BLM15HD182SN1 - Murata
Rint
10 kΩ Resistor 0402 5% 0.1 W
Internal pull-up resistor
Table 18: Example of ESD protection components for the RESET_N application circuit
Any external signal connected to the UART interface, SPI/IPC interface, I
2
S interfaces and GPIOs must be
tri-stated when the module is in power-down mode, when the external reset is forced low and during
the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits
and allow a proper boot of the module. If the external signals connected to the wireless module cannot
be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159,
or TS5A63157) between the two-circuit connections and set to high impedance during module power
down mode, when external reset is forced low and during power-on sequence.
1.7 RF connection
The ANT pin, provided by all LISA-U series modules, represents the main RF input/output used to transmit and
receive the 2G and 3G RF signal: the main antenna must be connected to this pad. The ANT pin has a nominal
characteristic impedance of 50 and must be connected to the antenna through a 50 transmission line to
allow transmission and reception of radio frequency (RF) signals in the 2G and 3G operating bands.
The ANT_DIV pin, provided by LISA-U230 modules, represents the RF input for the integrated diversity receiver:
the antenna for the Rx diversity should be connected to this pad. The ANT_DIV pin has a nominal characteristic
impedance of 50 and must be connected to the antenna for the Rx diversity through a 50 transmission line
to allow reception of radio frequency (RF) signals in the 2G and 3G operating bands.