Integration Manual

LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 59 of 160
Providing the TxD, RxD, RTS and CTS lines only (not using the complete V.24 link)
If the functionality of the DSR, DCD, RI and DTR lines is not required in the application, or the lines are not
available, the circuit with a 1.8 V Application Processor should be implemented as described in Figure 30:
 Connect the module DTR input line to GND, since the module requires DTR active (low electrical level)
 Leave DSR, DCD and RI lines of the module unconnected and floating
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
LISA-U series
(DCE)
15
TXD
12
DTR
16
RXD
13
RTS
14
CTS
9
DSR
10
RI
11
DCD
GND
0 Ω
0 Ω
TP
TP
0 Ω
0 Ω
TP
TP
Figure 30: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication (1.8V DTE)
If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 31.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
LISA-U series
(DCE)
15
TXD
12
DTR
16
RXD
13
RTS
14
CTS
9
DSR
10
RI
11
DCD
GND
0 Ω
0 Ω
TP
TP
0 Ω
0 Ω
TP
TP
1V8
B1 A1
GND
U1
B3A3
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR3
DIR2 OE
DIR1
VCC
B2 A2
B4A4
DIR4
Figure 31: UART interface application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC4T774 - Texas Instruments
Table 26: Component for UART application circuit with partial V.24 link (5-wire) in DTE/DCE serial communication (3.0 V DTE)
If only TxD, RxD, RTS and CTS lines are provided, as implemented in Figure 30 and in Figure 31, the procedure
to enable power saving depends on the HW flow-control status. If HW flow-control is enabled (AT&K3, that is