Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 61 of 160
If a 3.0 V Application Processor is used, proper voltage translator must be utilized, as described in Figure 33.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
DTR
DSR
RI
DCD
GND
LISA-U series
(DCE)
15
TXD
12
DTR
16
RXD
9
DSR
10
RI
11
DCD
GND
0 Ω
0 Ω
TP
TP
1V8
B1 A1
GND
U1
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR1
DIR2 OE
VCC
B2 A2
RTS
CTS
13
RTS
14
CTS
0 Ω
TP
TP
Figure 33: UART interface application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC2T245 - Texas Instruments
Table 27: Component for UART application circuit with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
If only TxD and RxD lines are provided, as described in Figure 32 and in Figure 33, and HW flow-control is
disabled (AT&K0), the power saving will be enabled by AT+UPSV=1. The module enters active-mode 20 ms after
a low-to-high transition on the TxD input line, and the recognition of the subsequent characters is guaranteed
until the module is in active-mode.
Data delivered by the DTE can be lost using this configuration and the following settings:
o HW flow-control enabled in the module (AT&K3, that is the default setting)
o Module power saving enabled by AT+UPSV=1
o HW flow-control disabled in the DTE
In this case the first character sent when the module is in idle-mode will be a wake-up character and
won’t be a valid communication character (refer to chapter 1.9.1.3 for the complete description).
If power saving is enabled the application circuit with the TxD and RxD lines only is not recommended.
During command mode the DTE must send to the module a wake-up character or a dummy “AT”
before each command line (refer to chapter 1.9.1.3 for the complete description), but during data mode
the wake-up character or the dummy “AT” would affect the data communication.