Integration Manual

LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 65 of 160
DC supply connected to the VCC pin to start the module firmware upgrade (see Firmware Update
Application Note [17]).
If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected,
but it is highly recommended to provide direct access to the lines for execution of firmware upgrade and
for debug purpose.
1.9.4 SPI interface
SPI is a master-slave protocol: the module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface
without specific configuration. The SPI-compatible synchronous serial interface cannot be used for FW upgrade.
The standard 3-wire SPI interface includes two signals to transmit and receive data (SPI_MOSI and SPI_MISO)
and a clock signal (SPI_SCLK).
LISA-U series modules provide two handshake signals (SPI_MRDY and SPI_SRDY), added to the standard 3-wire
SPI interface, implementing the 5-wire Inter Processor Communication (IPC) interface.
The purpose of the IPC interface is to achieve high speed communication (up to 26 Mb/s) between two
processors following the same IPC specifications: the module baseband processor and an external processor.
High speed communication is possible only if both sides follow the same Inter Processor Communication (IPC)
specifications.
Name
Description
Remarks
SPI_MISO
SPI Data Line.
Master Input, Slave Output
Module Output.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
SPI_MOSI
SPI Data Line.
Master Output, Slave Input
Module Input.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
Internal active pull-up to V_INT (1.8 V) enabled.
SPI_SCLK
SPI Serial Clock.
Master Output, Slave Input
Module Input.
Idle low (CPOL=0).
Up to 26 MHz supported.
Internal active pull-down to GND enabled.
SPI_MRDY
SPI Master Ready to transfer data control line.
Master Output, Slave Input
Module Input.
Idle low.
Internal active pull-down to GND enabled.
SPI_SRDY
SPI Slave Ready to transfer data control line.
Master Input, Slave Output
Module Output.
Idle low.
Table 30: SPI interface signals
The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if the lines are externally accessible on the application board.
Higher protection level can be achieved by mounting a low capacitance (i.e. less than 10 pF) ESD
protection (e.g. AVX USB0002 varistor array) on the lines connected to these pins, close to accessible
points.