Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 67 of 160
1.9.4.3 IPC communication examples
In the following, three IPC communication scenarios are described:
Slave initiated data transfer, with a sleeping master
Master initiated data transfer, with a sleeping slave
Slave ended data transfer
Slave initiated transfer with a sleeping master
Figure 36: Data transfer initiated by LISA-U series module (slave), with a sleeping application processor (master)
When the master is sleeping (idle-mode), the following actions happen:
1. The slave indicates the master that is ready to send data by activating SPI_SRDY
2. When the master becomes ready to send, it signalizes this by activating SPI_MRDY
3. The master activates the clock and the two processors exchange the communication header and data
4. If the data has been exchanged, the slave deactivates SPI_SRDY to process the received information. The
master does not need to de-assert SPI_MRDY as it controls the SPI_SCLK
5. After the preparation, the slave activates again SPI_SRDY and wait for SPI_SCLK activation. When the clock
is active, all the data is transferred without intervention. If there is more data to transfer (flag set in any of
the headers), the process will repeat from step 3
Master initiated transfer with a sleeping slave
Figure 37: Data transfer initiated by application processor (master) with a sleeping LISA-U series module (slave)
When the slave is sleeping (idle-mode), the following actions happen:
1. The Master wakes the slave by setting the SPI_MRDY line active
2. As soon as the slave is awake, it signals it by activating SPI_SRDY
SPI_MRDY
SPI_SRDY
DATA EXCHG
1
2
4
5
Header
Data
Header
3
SPI_MRDY
SPI_SRDY
DATA EXCHG
2
4
5
Header
Data
Header
3
1