Integration Manual
Table Of Contents
- Preface
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Power management
- 1.6 System functions
- 1.7 RF connection
- 1.8 (U)SIM interface
- 1.9 Serial communication
- 1.10 DDC (I2C) interface
- 1.11 Audio Interface
- 1.12 General Purpose Input/Output (GPIO)
- 1.13 Reserved pins (RSVD)
- 1.14 Schematic for LISA-U series module integration
- 1.15 Approvals
- 2 Design-In
- 2.1 Design-in checklist
- 2.2 Design Guidelines for Layout
- 2.2.1 Layout guidelines per pin function
- 2.2.2 Footprint and paste mask
- 2.2.3 Placement
- 2.3 Thermal aspects
- 2.4 Antenna guidelines
- 2.5 ESD precautions
- 3 Features description
- 4 Handling and soldering
- 5 Product Testing
- Appendix
- A Migration to LISA-U2 series wireless modules
- B Glossary
- Related documents
- Revision history
- Contact
LISA-U series - System Integration Manual
3G.G2-HW-10002-A3 Preliminary System description
Page 69 of 160
LISA-U series
(SPI slave)
MOSI
Application Processor
(SPI master)
MISO
SCLK
Interrupt
GPIO
GND
56
SPI_MOSI
59
SPI_MRDY
57
SPI_MISO
55
SPI_SCLK
58
SPI_SRDY
GND
Figure 39: IPC Interface application circuit
If direct access to the USB or the UART interfaces of the module is not provided, it is recommended to
provide direct access to the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY lines of the
module for debug purpose: testpoints can be added on the lines to accommodate the access and a 0 Ω
series resistor must be mounted on each line to detach the module pin from any other connected
device.
If the SPI/IPC interface is not used, the SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_MRDY, SPI_SRDY pins
can be left unconnected.
Any external signal connected to the SPI / IPC interface must be tri-stated when the module is in power-
down mode, when the external reset is forced low and during the module power-on sequence (at least
for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If
the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital
switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit
connections and set to high impedance during module power down mode, when external reset is forced
low and during power-on sequence.
1.9.5 MUX Protocol (3GPP 27.010)
LISA-U series modules have a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer Protocol [7],
available either on the UART or on the SPI physical link. The USB interface doesn’t support the multiplexer
protocol.
This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the
module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the used
physical link (UART or SPI): the user can concurrently use AT command interface on one MUX channel and
Packet-Switched / Circuit-Switched Data communication on another MUX channel. The multiplexer protocol can
be used on one serial interface (UART or SPI) at a time. Each session consists of a stream of bytes transferring
various kinds of data such as SMS, CBS, PSD, GPS, AT commands in general. This permits, for example, SMS to
be transferred to the DTE when a data connection is in progress.
The following virtual channels are defined:
Channel 0: control channel
Channel 1 – 5: AT commands /data connection
Channel 6: GPS tunneling
All LISA-U2 series modules versions except LISA-U200-00 provide an additional channel:
Channel 7: SIM Access Profile dedicated port
For more details please refer to GSM Mux implementation Application Note [15].