User's Manual

3300-Watt VHF Low Band Transmitter Chapter 4, Circuit Descriptions
335B, Rev. 0 4-2
mode signals (hum) that may occur on
its input leads. The composite audio
input signal is applied to the amplifier
U2B whose gain is controlled by the
composite audio gain pot R17. The
composite audio signal is then connected
to the summing point at U2D pin 13.
4.1.1.3 Subcarrier Audio Input
The third possible input to the board is
the subcarrier audio (SCA) input at the
BNC jack J4. The SCA input has an input
impedance of 75Ω that can be eliminated
by removing the jumper W2 from J14.
The SCA input is bandpass filtered by
C66, C14, R22, C15, C67, and R23 and
fed to the buffer amplifier U3A pin 3.
The amplified signal is then applied
though the SCA gain pot R24 to the
summing point at pin 13 of U2D.
4.1.1.4 Audio Modulation of the VCO
The balanced audio or the composite
audio and/or the SCA audio signals, are
fed to the common junction of resistors
R14, R20, and R27 that connect to the
summing point at pin 13 of the amplifier
U2D. The output audio signal at pin 14
of U2D is typically .8 Vpk-pk at a ±25-
kHz deviation with a balanced audio input
or .8 Vpk-pk at ±75-kHz deviation with a
composite audio input, as measured at
TP1. This audio signal is applied to the
VCO U10. A sample of the deviation
level is amplified, detected by U7A and
U7B, and connected to J10 on the board,
which is cabled to the front panel meter
through the transmitter control board.
The audio is applied through C64, a
frequency response adjustment, to CR13
to CR16, which are varactor diodes that
frequency modulate the audio signal onto
the generated 4.5-MHz signal in U10.
U10 is the 4.5-MHz VCO that generates
the 4.5-MHz continuous wave (CW)
signal. The output frequency of this
signal is maintained and controlled by the
correction voltage output of the PLL IC
U5. The audio-modulated, 4.5-MHz
signal is fed to amplifiers U11A and
U11B. The output of U11B is connected
to the 4.5-MHz output jacks at J7 and J8.
4.1.1.5 Phase Lock Loop (PLL) Circuit
A sample of the signal from the 4.5-MHz
aural VCO at the output of U11A is
applied to the PLL IC U5 pin 1, the F
in
connection. In U5, the signal is divided
down to 50 kHz and is compared to a 50-
kHz reference signal. The 50-kHz
reference signal is a divided-down
sample of the visual IF, 45.75-MHz signal
generated on the IF carrier oven
oscillator board, that is applied to pin 27,
the oscillator in connection, on the PLL
chip through jack J6 on the board. These
two 50-kHz signals are compared in the
IC and the f
V
output at pin 8 and the f
R
output at pin 7 are applied to the
differential amplifier U3B. The output of
U3B is fed back through CR17 to the 4.5-
MHz VCO IC U10, which sets up a PLL
circuit, therefore any change in frequency
will be corrected by the AFC error
voltage. The 4.5-MHz VCO, using the
PLL circuit, will maintain the extremely
accurate 4.5-MHz separation between the
visual 45.75 MHz and aural 41.25 MHz IF
signals.
The PLL chip U5 also contains an internal
lock detector that indicates the status of
the PLL circuit. When U5 is in a "locked"
state, pin 28 goes high and causes the
green LED DS1 to illuminate. If the 4.5-
MHz VCO and the 45.75-MHz oscillator
become "unlocked," out of the capture
range of the PLL circuit, pin 28 of U5 will
go to a logic low and cause the red LED
DS2 to light. A mute output signal from
Q3 (unlock mute) will be applied to jack
J9. This mute is connected to the
transmitter control board.
4.1.1.6 Voltage Requirements
The ±12 VDC needed for the operation of
the board enters through jack J1. The
+12 VDC is connected to J1-3 and
filtered by L2, C3, and C4 before it is
connected to the rest of the board. The