User's Manual

3300-Watt VHF Low Band Transmitter Chapter 4, Circuit Descriptions
335B, Rev. 0 4-4
video that is split off from the main video
path at the emitter of Q3. The video
sample is buffered by U3A and connected
to U4A. The level at which the tip of sync
is clamped, approximately -1.04 VDC, as
measured at TP2, is set by the voltage-
divider network connected to U4A. If the
video level changes, the sample applied
to U4A changes. If the jumper W7 on J4
is in the Clamp-On position, the voltage
from the clamp circuit that is applied to
the summing circuit at the base of Q2 will
change and bring the sync tip level back
to approximately -1.04 VDC. Q7 will be
turned off and on by the peak of sync
voltage level that is applied to U4A. The
capacitors C14, C51, C77, and C41 will
charge or discharge to the new voltage
level, which biases U3B more or less,
through the jumper W7 on J4 when in
the Auto Clamp-On position. U3 will
increase or decrease its output, as
needed, to bring the peak of sync back to
the correct level that is set by R152 and
R12. This voltage level is applied
through U3B to Q2. In the Manual
position, jumper W7 on J4 is in the
Clamp-Off position, between pins 1 and
2, and the adjustable resistor R41
provides the manual clamp bias
adjustment for the video that connects to
Q2.
The Jumper W6 on jack J35 must be in
the Normal position, between pins 2 and
3, for the clamp circuit to operate with a
normal non-scrambled signal. If a
scrambled signal is used, the tray is
operated with jumper W6 in the Encoded
position, connected between pins 1 and
2.
The clamp circuit is set by adjusting the
depth of modulation pot R152 for the
correct depth of modulation as measured
at TP2. Depending on the input video
level, the waveform as measured at TP2
may not be 1 Vpk-pk. If W7 on J4 is
moved to the Clamp-Off (Manual)
position, between pins 1 and 2, the
clamp level is adjusted by R41 and will
not automatically be clamped to the set
level.
The output of buffer amplifier U3A drives
the sync tip clamp circuit consisting of
the differential amplifier U4A, FET Q7,
and buffer amplifier U3B. U4A is biased
by R124, R125, R184, R152, and R126
so that the clamped voltage level at the
peak of sync is approximately -1.04 VDC
as measured at TP2.
4.1.2.3 Main Video Signal Path (Part 2 of
2)
The clamped video from Q2 is connected
to the white clipper circuit Q3. Q3 is
adjusted by R20 and set to prevent video
transients from overmodulating the video
carrier. The clamped video is connected
to the sync clipper circuit Q4, which is
adjusted by R24. Q4 limits the sync to
-40 IRE units. The corrected video
output of the emitter follower Q4 is wired
to the unity gain amplifier U2A that
provides a low impedance, clamped video
output at pin 1, which can be measured
at TP2.
4.1.2.4 Visual Modulator Circuit
The clamped video signal from U2A is
split. One part connects to a metering
circuit, consisting of U20 and associated
components, which produces a video
output sample, white level, at J8-6 that
connects through the transmitter control
board to the front panel meter for
monitoring. The other clamped video
path from U2A is through a sync stretch
circuit that consists of Q5 and Q6. The
sync stretch circuit contains R48 that
adjusts the sync stretch magnitude
(amount) and R45 that adjusts the cut-in
point. This sync stretch adjustment
should not be used to correct for output
sync problems, but it can be used for
input video sync problems. The output of
the sync stretch circuit connects to pin 5,
the I input of mixer Z1.
The video signal is heterodyned, in mixer
Z1, with the 45.75 MHz visual IF CW
signal. The visual IF CW signal enters
the board at jack J15 and is connected to
U9, where it is amplified and wired to pin