User's Manual
3300-Watt VHF Low Band Transmitter Chapter 4, Circuit Descriptions
335B, Rev. 0 4-26
(1145-1201) that generates a stable
frequency reference signal of
approximately 100 MHz. The channel
oscillator assembly is an enclosure that
provides temperature stability for the
crystal oscillator. An SMA output at jack
J1 and an RF sample at BNC connector
jack J2 are also part of the assembly.
Adjustments can be made through access
holes in the top cover of the assembly.
These adjustments are set at the factory
and should not be tampered with unless
it is absolutely necessary and the proper,
calibrated equipment is available. R1 is
the temperature adjustment; C11 is the
course-frequency adjustment; C9 is the
fine-frequency adjustment; and C6, C18,
L2, and L4 are adjusted for the maximum
output level at the frequency as
measured at jack J1.
The +12 VDC for the assembly enters
through FL1 and the circuit ground
connection is made at E1.
4.1.10.1 (A14) (Optional) VCXO
Assembly, Dual Oven (1145-1206;
Appendix D)
NOTE: If the precise frequency kit is not
present in your transmitter, the Channel
Oscillator Assembly (1145-1202) will be
used.
The VCXO assembly contains the VCXO
channel oscillator board (1145-1204),
which generates a stable frequency
reference signal of approximately 100
MHz. The VCXO channel oscillator
assembly is an enclosure that provides
temperature stability for the crystal
oscillator. An SMA output at jack J1
feeds the x2 multiplier board and an RF
sample at BNC connector jack J2
provides an oscillator sample to the front
panel of the VHF exciter tray.
Adjustments are provided through access
holes in the top cover of the assembly.
These adjustments are set at the factory
and should not be adjusted unless it is
absolutely necessary and the properly
calibrated equipment is available. R1 is
the temperature adjustment; C11 is the
course frequency adjustment; and C6,
C18, L2, and L4 are adjusted for
maximum output level at frequency as
measured at jacks J1 or J2. The AFC
voltage, which is fed to FL2 from the
precise frequency control tray, is the fine
frequency adjustment.
The +12 VDC for the assembly enters
through FL1 and the circuit ground
connection is made at E1.
4.1.11 (Optional) (A13) EEPROM FSK
Identifier Board (1265-1308;
Appendix D)
The (Optional) FSK identifier board, with
EEPROM, generates a morse code
identification call sign by sending a bias
voltage to the IF attenuator board to
amplitude modulate the aural carrier.
This gives the station a means of
automatically repeating its identification
call sign, at a given time interval, to
meet FCC requirements.
The starting circuit is made up of U1B
and U1D, which are connected as a
flip-flop, with gate U1A used as the set
flip-flop. U1A automatically starts the
flip-flop each time U3 completes its
timing cycle. At the start of a cycle, U1B
enables clock U2. U2 applies the clock
pulses that set the speed, which is
adjusted by R2, for when the
identification code is sent to 12-bit binary
counter U4. R2, fully clockwise (CW), is
the fastest pulse train and R2, fully
counter-clockwise (CCW), is the slowest
pulse train. U4 provides binary outputs
that address EEPROM U5.
The scans in U4 will continue until the
field effect transistor (FET) Q1 is gated
on. The gate of Q1 is connected to pin
13 on U4, which is the maximum count
used in the EEPROM, and will provide a
reset pulse each time the binary counter
goes high on pin 13. The reset pulse,
when the drain of Q1 goes low, is applied
to the flip-flop and the timer U3, which