Assembly Instructions Chapter 4

10-kW UHF Transmitter with Chapter 4, Circuit
Feedforward Drive Descriptions
840A, Rev. 0 4-2
buffer amplifier U3A. The amplified signal
is then applied though SCA gain pot R24
to the summing point at pin 13 of U2D.
Audio Modulation of the VCO
The balanced audio, or the composite
audio and/or the SCA-buffered audio
signals, are fed to the common junction
of resistors R14, R20, and R27 that
connect to pin 13 of amplifier U2D. The
output audio signal at pin 14 of U2D is
typically .8 Vpk-pk at a ±25-kHz
deviation for balanced or .8 Vpk-pk at
±75-kHz deviation for composite as
measured at TP1. This signal is applied to
VCO U10. A sample of the deviation level
is amplified, detected by U7A and U7B,
and connected to J10 on the board. This
audio-deviation level is connected to the
front panel meter through the transmitter
control board.
The audio is connected to CR13 to CR16;
these are varactor diodes that frequency
modulate the audio signal onto the
generated 4.5-MHz signal in U10. U10 is
the 4.5-MHz VCO that generates the 4.5-
MHz continuous wave (CW) signal. The
output frequency of this signal is
maintained and controlled by the
correction voltage output of U5 PLL IC.
The audio-modulated, 4.5-MHz signal is
fed to amplifiers U11A and U11B. The
output of U11B is connected to the 4.5-
MHz output jacks at J7 and J8.
Phase Lock Loop (PLL) Circuit
A sample of the signal from the 4.5-MHz
aural VCO at the output of U11A is
applied to PLL IC U5 at the F
in
connection. In U5, the signal is divided
down to 50 kHz and is compared to a 50-
kHz reference signal. The reference
signal is a divided-down sample of the
visual IF, 45.75-MHz signal that is
applied to the oscillator-in connection on
the PLL chip through jack J6 on the
board. These two 50-kHz signals are
compared in the IC and the fV, and fR is
applied to the differential amplifier U3B.
The output of U3B is fed back through
CR17 to the 4.5-MHz VCO IC U10; this
sets up a PLL circuit. The 4.5-MHz VCO
will maintain the extremely accurate 4.5-
MHz separation between the visual and
aural IF signals; any change in frequency
will be corrected by the AFC error
voltage.
PLL chip U5 also contains an internal lock
detector that indicates the status of the
PLL circuit. When U5 is in a "locked"
state, pin 28 goes high and causes the
green LED DS1 to illuminate. If the 4.5-
MHz VCO and the 45.75-MHz oscillator
become "unlocked," out of the capture
range of the PLL circuit, pin 28 of U5 will
go to a logic low and cause the red LED
DS2 to light. A mute output signal from
Q3 (unlock mute) will be applied to jack
J9. This mute is connected to the
transmitter control board.
Voltage Requirements
The ±12 VDC needed for the operation of
the board enters through jack J1. The
+12 VDC is connected to J1-3 and
filtered by L2, C3, and C4 before it is
connected to the rest of the board. The -
12 VDC is connected to J1-5 and filtered
by L1, C1, and C2 before it is connected
to the rest of the board. +12 VDC is
connected to U8 and U9; these are 5-volt
regulator ICs that provide the voltage to
the U10 and U5 ICs.
4.1.1.2 (A5) Sync Tip Clamp/Modulator
Board (1265-1302; Appendix B)
The sync tip clamp/modulator board can
be divided into five circuits: the main
video circuit, the sync tip clamp circuit,
the visual modulator circuit, the aural IF
mixer circuit, and the diplexer circuit.
The sync tip clamp/modulator board
takes the baseband video or 4.5-MHz
composite input that is connected to the
video input jack (either J1 or J2, which
are loop-through connected), and
produces a modulated visual IF + aural
IF output at output jack J20 on the
board. The clamp portion of the board