Assembly Instructions Chapter 4

10-kW UHF Transmitter with Chapter 4, Circuit
Feedforward Drive Descriptions
840A, Rev. 0 4-3
maintains a constant peak of sync level
over varying average picture levels
(APL). The modulator portion of the
board contains the circuitry that
generates an amplitude-modulated
vestigial sideband visual IF signal output
that is made up of the baseband video
input signal (1 Vpk-pk) modulated onto
an externally generated 45.75-MHz IF
carrier frequency. The visual IF signal
and the aural IF signal are then
combined in the diplexer circuit to
produce the visual IF + aural IF output
that is connected to J20, the IF output
jack of the board.
Main Video Signal Path (Part 1 of 2)
The baseband video or the 4.5-MHz
composite input connects to the board at
J2. J2 is loop-through connected to J1
and terminated to 75 watts if jumper W4
is on jack J3. With jumper W4 removed,
the input can be connected to another
transmitter through J1; J1 is loop-
through connected to J2.
Test point TP1 is provided to monitor the
level of the input. The input is fed to the
non-inverting and inverting inputs of
U1A, a differential amplifier that
minimizes any common-mode hum that
may be present on the incoming signal.
Diodes CR1 to CR4 form a voltage-limiter
network in which, if the input voltages
exceed the supply voltages for U1A, the
diodes conduct, preventing damage to
U1A. CR1 and CR3 conduct if the input
voltage exceeds the negative supply and
CR2 and CR4 conduct if the input voltage
exceeds the positive supply voltage.
The video output of U1A is connected to
J22 on the board. Normally, the video at
J22 is jumpered to J27 on the board. If
the 4.5-MHz composite input kit is
purchased, the 4.5-MHz composite signal
at J22 connects to the external composite
4.5-MHz filter board and the 4.5-MHz
bandpass filter board. These two boards
provide the video-only signal to J27 and
the 4.5-MHz intercarrier signal to J28
from the 4.5-MHz composite input. The
video through the video gain pot R12
(adjusted for 1 Vpk-pk at TP2) connects
to amplifier U1B.
The output of U1B, if the delay equalizer
board is present in the tray, connects the
video from J6, pin 2, to the external
delay equalizer board and back to the
sync tip clamp/modulator board at J6,
pin 4. If the delay equalizer is not
present, the video connects through
jumper W1 on J5, pins 1 and 2. The
delay equalizer board plugs directly to J6
on the sync tip clamp/modulator board.
The video from J6, pin 4, is then
connected through jumper W1 on J5,
pins 2 and 3, to the amplifier Q1. The
output of Q1 connects to Q2; the base
voltage of Q2 is set by the DC offset
voltage output of the sync tip clamp
circuit.
Sync Tip Clamp Circuit
The automatic sync tip clamp circuit is
made up of U4A, Q7, U3B, and
associated components. The circuit
begins with a sample of the clamped
video that is split off from the main video
path at the emitter of Q3. The video
sample is buffered by U3A and connected
to U4A. The level at which the tip of sync
is clamped, approximately -1.04 VDC as
measured at TP2, is set by the voltage-
divider network connected to U4A. If the
video level changes, the sample applied
to U4A changes. If jumper W7 on J4 is in
the Clamp-On position, the voltage from
the clamp circuit that is applied to the
summing circuit at the base of Q2 will
change; this will bring the sync tip level
back to approximately -1.04 VDC. Q7 will
be turned off and on according to the
peak of sync voltage level that is applied
to U4A. The capacitors C14, C51, C77,
and C41 will charge or discharge to the
new voltage level, which biases U3B
more or less, through jumper W7 on J4
in the Auto Clamp-On position. U3 will
increase or decrease its output, as
needed, to bring the peak of sync back to
the correct level as set by R152 and R12.
This voltage level is applied through U3B