Assembly Instructions Chapter 4

10-kW UHF Transmitter with Chapter 4, Circuit
Feedforward Drive Descriptions
840A, Rev. 0 4-4
to Q2. In the Manual position, jumper W7
on J4 is in the Clamp-Off position,
between pins 1 and 2, and adjustable
resistor R41 provides the manual clamp
bias adjustment for the video that
connects to Q2.
Jumper W6 on jack J35 must be in the
Normal position, between pins 2 and 3,
for the clamp circuit to operate with a
normal non-scrambled signal. If a
scrambled signal is used, the tray is
operated with jumper W6 in the Encoded
position, connected between pins 1 and
2. The clamp circuit is set by adjusting
depth of modulation pot R152 for the
correct depth of modulation as measured
at TP2.
Depending on the input video level, the
waveform as measured at TP2 may not
be 1 Vpk-pk. If W7 on J4 is moved to the
Clamp-Off (Manual) position, between
pins 1 and 2, the clamp level is adjusted
by R41 and will not automatically be
clamped to the set level. The output of
buffer amplifier U3A drives the sync tip
clamp circuit consisting of differential
amplifier U4A, FET Q7, and buffer
amplifier U3B. U4A is biased by R124,
R125, R184, R152, and R126 so that the
clamped voltage level at peak of sync is
approximately -1.04 VDC as measured at
TP2.
Main Video Signal Path (Part 2 of 2)
The clamped video from Q2 is connected
to white clipper circuit Q3. Q3 is adjusted
with R20 and set to prevent video
transients from overmodulating the video
carrier. The clamped video is connected
to sync clipper circuit Q4 (adjusted by
R24); Q4 limits the sync to -40 IRE units.
The corrected video connects to emitter
follower Q4 whose output is wired to
unity gain amplifier U2A and provides a
low-impedance, clamped video output at
pin 1.
Visual Modulator Circuit
The clamped video signal from U2A is
split. One part connects to a metering
circuit, consisting of U20 and associated
components, that produces a video
output sample at J8-6 and connects
through the transmitter control board to
the front panel meter for monitoring. The
other clamped video path from U2A is
through a sync-stretch circuit that
consists of Q5 and Q6. The sync-stretch
circuit contains R48; R48 adjusts the
sync stretch magnitude (amount) and
R45 adjusts the cut-in. This sync-stretch
adjustment should not be used to correct
for output sync problems, but it can be
used for video input sync problems. The
output of the sync-stretch circuit
connects to pin 5, the I input of mixer
Z1.
The video signal is heterodyned in mixer
Z1 with the visual IF CW signal (45.75
MHz). The visual IF CW signal enters the
board at jack J15 and is connected to U9,
where it is amplified and wired to pin 1,
the L input of mixer Z1. The adjustable
capacitor C78 and resistor R53 are set up
to add a small amount of incidental
carrier phase modulation (ICPM)
correction to the output of the mixer
stage to compensate for any non-
linearities generated by the mixer.
The modulated 45.75-MHz RF output of
mixer Z1 is amplified by U5 and is fed to
double-sideband visual IF output jack
J18. The level of this output jack is
adjusted by R70. J18 is the visual IF
loop-through output jack that is normally
jumpered to J19 on the board. If the
optional visual IF loop-through kit is
purchased, the visual is connected out of
the board to any external IF processor
trays.
After any external processing, the
modulated visual IF, double-sideband
signal re-enters the board through J19.
The visual IF from J19 is amplified by
U10 and U11 and routed through the
vestigial sideband filter network,