Assembly Instructions Chapter 4

10-kW UHF Transmitter with Chapter 4, Circuit
Feedforward Drive Descriptions
840A, Rev. 0 4-41
remains below this reference level, U1,
pin 2, will go low and the low is applied
to NAND gate U2, pins 1 and 2. U2, pin
3, will go high and the high is applied to
NAND gate U2, pin 5. Because J4-1 is
jumpered to J4-4, the input sample of
the low screen current is also applied to
U1, pin 7. R12 sets the lower limit trip
point for this section of the IC. If the
screen current decreases below this
reference level, U1, pin 1, will go low and
the low is applied to NAND gate U2, pin
6. At this point, U2, pin 5, is high and U2,
pin 6, is low, causing NAND gate U2, pin
4, to be high. A high output from the
board at J2, pin 5, is a screen current
fault condition.
A sample of the grid current is applied to
J1-4 of the board. From J1-4, the current
sample is connected to comparator U1,
pin 9. R18 sets the upper limit trip point
for this section of the IC. If the grid
current remains below this reference
level, U1, pin 14, will go low and the low
is applied to NAND gate U2, pins 8 and 9.
U2, pin 10, will go high and the high is
applied to NAND gate U2, pin 12.
Because J1-3 is jumpered to J1-6, the
input sample of the grid current is also
applied to U1, pin 11. R25 sets the lower
limit trip point for this section of the IC.
If the grid current remains above this
reference level, U1, pin 13, will go high
and the high is applied to NAND gate U2,
pin 13. During normal operation, U2, pin
12, and U2, pin 13, are both high. This
causes NAND gate U2, pin 11, to be low.
A low output from the board at J2, pin 4,
occurs during normal operation.
If the grid current sample applied to
comparator U1, pin 9, increases above
the upper limit trip point set by R18, U1,
pin 14, will go high. The high is applied
to NAND gate U2, pins 8 and 9. U2, pin
10, will go low and the low is applied to
NAND gate U2, pin 12. Because J1-3 is
jumpered to J1-6, the input sample of
the grid current is also applied to U1, pin
11. R25 sets the lower limit trip point for
this section of the IC. If the grid current
remains above this reference level, U1,
pin 13, will go high and the high is
applied to NAND gate U2, pin 13. U2, pin
12, is now low and U2, pin 13, is high;
this causes NAND gate U2, pin 11, to be
high. A high output from the board at J2,
pin 4, is a grid current fault condition.
The grid current sample is applied to J1-4
on the board and jumpered to J1-7. From
J1-4, the current sample is connected to
comparator U1, pin 9. R18 sets the upper
limit trip point for this section of the IC.
If the grid current remains below this
reference level, U1, pin 14, will go low
and the low is applied to NAND gate U2,
pins 8 and 9. U2, pin 10, will go high and
the high is applied to NAND gate U2, pin
12. Because J1-3 is jumpered to J1-6,
the input sample of the low grid current
is also applied to U1, pin 11. R25 sets the
lower limit trip point for this section of
the IC. If the grid current decreases
below this reference level, U1, pin 13,
will go low and the low is applied to
NAND gate U2, pin 13. At this point, U2,
pin 12, is high and U2, pin 13, is low,
causing NAND gate U2, pin 11, to be
high. A high output from the board at J2,
pin 4, is a grid current fault condition.
4.3 (A3) High-Voltage Power Supply
Assembly, 208/240 VAC (1068022;
Appendix A)
4.3.1 Current Metering Board (1084-
1205; Appendix B)
The current metering board takes a
voltage sample from an operating power
supply and provides an output level that
can be used in a current metering circuit.
The sample voltage input is applied at J1,
pins 1 and 3, and is fed to a pi-
attenuator network consisting of R1, R2,
R3, and R4. The value of R1 can be
changed to increase or lower the value of
the input voltage for the desired current
meter reading. R3 can be adjusted to
calibrate the output level and display an
accurate meter reading of the current
value.