Assembly Instructions Chapter 4

10-kW UHF Transmitter with Chapter 4, Circuit
Feedforward Drive Descriptions
840A, Rev. 0 4-8
Main IF Signal Path (Part 1 of 3)
The selected visual + aural IF input (0
dBm) signal is split, with one half of the
signal entering a bandpass filter that
consists of L3, L4, C4, L5, and L6. This
bandpass filter can be tuned with C4 and
is substantially broader than the IF signal
bandwidth. It is used to slightly steer the
frequency response of the IF to make up
for any small discrepancies in the
frequency response in the stages that
precede this point. The filter also serves
the additional function of rejecting
unwanted frequencies that may occur if
the tray cover is off and the tray is in a
high RF environment (if this is the case,
the transmitter will have to be serviced
with the tray cover off in spite of the
presence of other RF signals). The
filtered IF signal is fed through a pi-type
matching pad consisting of R2, R3, and
R4 to the pin-diode attenuator circuit
consisting of CR1, CR2, and CR3.
Input Level Detector Circuit
The other part of the split IF input is
connected through L2 and C44 to U7; U7
is an IC amplifier that is the input to the
input level detector circuit. The amplified
IF is fed to T4; T4 is a step-up
transformer that feeds diode detector
CR14. The positive-going detected signal
is then low-pass filtered by C49, L18, and
C50. This allows only the video with
positive sync to be applied through
emitter follower Q1. The signal is then
connected to detector CR15 to produce a
peak-sync voltage that is applied to op-
amp U9A. There is a test point at TP3
that provides a voltage reference check
of the input level. The detector serves
the dual function of providing a reference
that determines the input IF signal level
to the board and also serves as an input
threshold detector.
The input threshold detector prevents the
automatic level control from reducing the
attenuation of the pin-diode attenuator to
minimum (the maximum signal) if the IF
input to the board is removed. The ALC,
video loss cutback, and the threshold
detector circuits will only operate when
jumper W3 on jack J6 is in the Auto
position, between pins 1 and 2. Without
the threshold detector, and with the pin-
diode attenuator at minimum, when the
signal is restored it will overdrive the
stages following this board.
As part of the threshold detector
operation, the minimum IF input level at
TP3 is fed through detector CR15 to op-
amp IC U9A, pin 2. The reference voltage
for the op-amp is determined by the
voltage divider that consists of R50 and
R51 (off the +12 VDC line). When the
detected-input signal level at U9A, pin 2,
falls below this reference threshold
(approximately 10 dB below the normal
input level), the output of U9A at pin 1
goes to the +12 VDC rail. This high is
connected to the base of Q2. At this
point, Q2 is forward biased and creates a
current path from the -12 VDC line and
through red LED DS1, the input level
fault indicator, which becomes lit, resistor
R54, and transistor Q2 to +12 VDC. The
high from U9A also connects through
diode CR16 to U9B, pin 5, whose output
at pin 7 goes high. The high connects
through range adjust pot R74 to J20,
which connects to the front panel-
mounted power adjust pot. This high
connects to U10A, pin 2, and causes it to
go low at output U10A, pin 1. The low is
applied through jumper W3 on J6 to the
pin-diode attenuator circuit that cuts
back the IF level and, therefore, the
output power level, to 0. When the input
signal level increases above the threshold
level, the output power will raise, as the
input level increases, until normal output
power is reached.
The video input level at TP3 is also fed to
a sync-separator circuit, consisting of IC
U8, CR17, Q3, and associated
components, and then to a comparator
circuit made up of U9C and U9D. The
reference voltage for the comparators is
determined by a voltage divider
consisting of R129, R64, R65, R66, and
R130 (off the -12 VDC line). When the