User's Manual

Innovator CU5-1800BTD/BRD ATSC Transmitter/ Board Descriptions
Regenerative Translator
Instruction Manual, Rev. 0 42
Circuit Descriptions of Boards in the CU5, CU30, CU50, CU100 & CU125 Systems
(A1) 8 VSB Demodulator Board (1308275) - Only used with BRD operation
Overview
The 8 VSB demodulator assembly receives an off air 8 VSB signal on any VHF or UHF
channel and demodulates this to an MPEG-2 transport stream that is per the SMPTE-
310M standard. The input to the assembly is at an “F” style connector on the shielded
tuner and can be at a level of –8 to –78 dBm. The tuner (TU1) down converts the RF
channel to a 44 MHz IF signal. This signal is the input to the digital receiver chip U1.
The digital receiver chip subsequently decodes the IF and delivers an MPEG-2 transport
stream on a parallel data bus to a programmable logic array, U8. U8 clocks the
asynchronous MPEG data from the receiver chip and outputs a synchronous data stream
at a 19.39 MHz rate to buffer/driver U11. U11 subsequently drives the output at J13 to
a lower level that is AC coupled out of the board.
Microcontroller Functions
A microcontroller, U17, is provided on this assembly to supervise the operation of the
receiver chip and the tuner. In addition, the microcontroller also interfaces to the front
panel LCD display via connector J24 and pushbutton interface on J27. On power up, the
microcontroller sets the tuner to the last channel that was selected when the unit was
powered down. In addition, the microcontroller also configures the digital receiver to
operate as an 8 VSB receiver. The communication between all of the devices on this
board is via an I2C serial bus that is local to this board.
Jumper and DIP Switch Settings
This board can be used in various assemblies. When this assembly is installed in the
Innovator CXB product, the jumper on J26 should be placed between pins 2 and 3.
There are two other jumpers in this assembly, on J7 and J8. Both of these jacks should
have the jumper placed between pins 2 and 3 for normal operation.
The DIP switch on this board is reserved for future use and should remain set with all
switches in the OFF position.
(A2) Digital Modulator Board (1304883), Part of the Digital Modulator
w/Power Conditioner (1309629)
SMPTE-310 Input
The digital modulator board accepts a SMPTE-310 input at the SMA connector J42 from
the 8 VSB demodulator board in a BRD system or directly from the RF input jack on the
rear of the tray in an BTD system. This input is applied to a high speed window
comparator U21 that adjusts the level to a low voltage TTL signal to be used by the
Altera FPGA, U3. The SMPTE-310 signal is input to the FPGA to recover the clock and
the data. A portion of the clock and recovery circuit is performed by a high-speed
comparator, U17, which functions as an external delay circuit.