User's Manual

300-Watt Digital UHF Transmitter Chapter 5, Detailed Alignment Procedures
DT830A, Rev. 1 5-9
5.3.1 (A11) VSB Modulator Interface
Board (1561-1205; Appendix D)
The VSB modulator interface board
interfaces the external MPEG source to
the 8-VSB symbol generator board. The
interface board receives MPEG either at
J11 in SMPTE format, at J1 in differential
emitter-to-coupler logic (ECL) format, or
at J2 in differential TTL format, and
converts it to single-ended transistor-to-
transistor (TTL) in the form of data (J10)
and a clock (J3). The jumpers J13 and
J14 on this card select between the
various input formats. These jumper
settings are outlined in the discussion on
the 8-VSB modulator in Chapter 2 of this
manual. Jumpers J4 through J7 were
used during the initial design of the
board and have been preset at the
factory. These four jumpers should all
be placed in positions 1-2 with the
exception of jumper J6, which should be
placed in position 2-3. Jumper block J15
was also used in the initial design of the
board and should be set to position 3.
In addition, if required, this card can be
used for a future parallel interface that
is either in a TTL or an ECL format. The
interface will utilize the PLL Locked LED
at the bottom, right-hand corner of the
board; this LED will not illuminate with
the existing interfaces. Test connector
J8 will also be used, as needed, for
future parallel interfaces.
5.3.2 (A4) VSB Symbol Generator
Board (1049396; Appendix D)
The symbol generator board takes the
MPEG data and clock signals from the
interface card and performs the digital
signal-processing functions outlined in
the ATSC specification for 8-VSB
modulation. These functions involve
data randomization, the Reed Solomon
encoder, data interleaver, and the trellis
encoder. These functions are
implemented in programmable logic chip
U1 on the symbol generator card. In
addition, this card performs the linear
equalization function. This function is
implemented in U14.
The output of this card is symbol data
that has been equalized. The data is
available at J25 in the form of ten data
lines and a 32.28-MHz clock. In addition,
the microcontroller data and address
bus is available at this output connector.
The LCD display and the switch panel
are also controlled by the symbol
generator card. The interface to the LCD
display is provided at J20 and the
interface to the switch panel is provided
at J21. The RS-232 interface to Port A is
provided at J19 on this card. This
interface is wired to the rear of the tray
and is used to load the linear equalizer
and perform adaptive equalization. The
Port B serial interface is wired through
connector J4 on this card.
Note: The symbol generator board
contains jumper blocks that have
been set at the factory. No
additional alignment is required to
achieve normal operation.
In the event that the board becomes
incorrectly aligned, the jumpers on the
card should be placed in the
configurations shown in Table 5-4.