User's Manual

Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT835A, Rev. 1 4-2
which has a jumper connected between
Pins 1 & 2, that provides the Interlock
to the Exciter needed to operate the
Transmitter. If the Jumper is missing,
the Transmitter will not switch to
Operate. If remote connections are
made to the Transmitter, they should
be made through the plugs provided in
the Installation Material as noted on the
Interconnect Drawing (1056919 or
1278-8400) for the Single UHF Exciter.
4.1.3 AC Input
The Single UHF Exciter Assembly needs
an AC input of 208/240 VAC at 20
Amps. The AC Input to the Single UHF
Exciter Assembly connects to (A8) the
AC Distribution Assembly, UHF Exciter
Assembly (1245-1500) located in the
right, center rear of the Cabinet. The
Assembly contains the 4 Terminal Block
(TB1) to which the 208/240 VAC
connects. Line 1 to TB1-1, Line 2 to
TB1-3 and Safety Ground to TB1-2.
The AC Distribution Panel contains one
Circuit Breaker that supplies the AC to
the rest of the Single Exciter Assembly.
The Input AC is connected to (CB1) the
Main AC Circuit Breaker (20 Amps).
The output of CB1 has three MOVs,
VR1, VR2 and VR3, connected to it, one
connected from each leg of the Input
AC to ground and one across the two
legs. The AC output of CB1 connects to
A1 and A2 which are IEC Outlet Strips.
The (A1) Exciter 1 and the (A4)
Variable Gain/Phase Tray plug into the
(A1) IEC Outlet Strip. The (A5)
Variable Gain/Phase Tray, the (A8)
Metering Panel and the 8 VSB
Modualtor Tray plug into the (A2) IEC
Outlet Strip.
When the Circuit Breaker CB1,
mounted on the AC Distribution
Assembly, is switched On, +12 VDC
from the Exciter, is supplied to each of
the Amplifier Array Cabinets for the
operation of the LED Status Indicators
in each of the UHF Amplifier Trays.
4.2 (A19) DM8-R Digital Modulator
(1306978; Appendix C)
4.2.1 (A1) DM8 Modulator Board
(1304883; Appendix D)
4.2.1.1 SMPTE-310 Input
The DM8-R modulator accepts a
SMPTE-310 input the BNC Jack J2
located on the rear panel of the tray.
This input is connected to J42 on the
Digital Modulator Board via a RG-179
cable. This input is applied to a high
speed window comparator that adjusts
the level to a low voltage TTL signal to
be used by the Altera FPGA, U3. The
SMPTE-310 signal is input to the FPGA
to recover the clock and the data. A
portion of the clock and recovery
circuit is performed by a high speed
comparator, U17, that functions as an
external delay circuit.
4.2.1.2 Channel Coder
The FPGA subsequently uses the
SMPTE-310 clock and data as the input
to the channel coder contained inside
the FPGA. The channel coder is a
series of DSP blocks defined by the
ATSC standard for 8 VSB data
transmission. These blocks include the
data randomizer, Reed Solomon
Encoder, data interleaver, trellis coder,
and sync insertion. The channel
coder portion inside the FPGA
generates the 8 distinct levels in an 8
VSB transmitter. These levels are
subsequently input to a linear
equalizer that provides for frequency
response correction in the
transmission path. The linear
equalizer is a 67 tap FIR filter that is
loaded with tap values from the
microntroller, U1, located on this
board. The output of the linear
equalizer is then input to two pulse
shaping filters, an in phase (I) and a
quadrature (Q) filter that are also
located inside the FPGA. The pulse
shaping filters are FIR filters that have
fixed tap values that are preset inside