User's Manual

Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT835A, Rev. 1 4-6
applies the external 10-MHz reference
signal to U1 for use in the PLL circuits.
Internal 10-MHz Reference Circuitry
The internally generated 10-MHz
reference signal connects from jack J7
on the board to pins 3 and 6 of relay
K1. If the external 10-MHz reference is
missing, or the interlock is not present
at J8, pin 1, the relay is de-energized.
The internally generated 10-MHz
reference connects through the closed
contact of the relay from pin 3 to pin 1
to amplifier U1. The externally
generated 10-MHz signal from jack J2
connects through the closed contact of
the relay from pin 5 to pin 7 to R10,
the 51-Ω load.
Sample Input Circuitry
A sample of the signal from the UHF
generator board connects to SMA jack
J9, the sample input on the board. The
signal is amplified by U8 and coupled to
U9, a divide by 20/21 IC. A sample of
the output of U8 is connected to J10,
the sample output jack on the board,
which is typically connected to the front
panel of the tray.
Comparator Phase Lock Loop Circuit
The selected 10-MHz reference
connects to amplifier IC U1 whose
output is split by the circuit consisting
of L3, L4, and R8. A sample of the 10-
MHz reference is cabled to jack J3, the
10-MHz output jack, which is connected
to J5 on the rear of the tray. The 10-
MHz reference connects to IC U4, a
divider PLL chip. The divided-down
sample of the 10-MHz reference, which
is measurable at TP2, connects from
pin 10 of U4 to pin 27 of U5.
The divided-down sample from U9 is
connected to U5, a divider comparator
IC, which divides this signal to a 50-
kHz reference. The 50-kHz references
are compared in the U5 IC to a 50-kHz
sample of the 10-MHz signal that is
generated from an external 10-MHz
reference input or internally from a 10-
MHz reference kit. The three DIP
switches, SW1, SW2, and SW3, are set
up to divide down the reference sample
input generated by the VCXO to 50
kHz. The reference is then compared to
the 50-kHz sample from the 10-MHz
input in the U5 IC.
The output of U5 at pins 7 and 8
connect to U6A, a differential
comparator, whose output is the
difference between the two 50-kHz
references which is the AFC voltage.
The AFC voltage is amplified by U6B
and connected to jack J4. W1 on J4
must be in the AFC auto position,
between pins 1 and 2, for the PLL
circuit to operate. With jumper W1
between pins 2 and 3 on J6, fixed bias,
the AFC bias is set by R12. The AFC
output at J6 on the board connects to
the VCXO on the UHF generator board.
The PLL circuit will maintain the very
accurate VCXO output because any
change in frequency will be corrected
by the AFC error voltage.
Lock Detector Circuit
IC chip U2 contains an internal lock
detector that indicates the status of the
PLL circuit. When U2 is in a locked
state, pin 3 and pin 7 go low; the low is
applied to Q1, which is biased off. With
Q1 off, pin 1 of J1 goes high and is
connected to the Lock LED on the LED
display board that lights. The low
applied to DS1, the Red Unlock LED,
causes it not to light.
If the 50 kHz from the 10-MHz
reference and the 50-kHz from the UHF
generator board become unlocked, out
of the capture range of the PLL, pins 2
and 6 of U2 go to a logic low; this
causes U2, pins 3 and 7, to go high.
The high connects to DS1, the red
Unlock LED, which lights, and to Q1
and Q2, which are biased on. When Q2
is biased on, it connects a low remote
unlock to jack J1, pin 4. With Q1 biased