User's Manual

Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT835A, Rev. 1 4-10
de-energized, it connects the receiver
IF input at J1, if present, to 50 watts.
When K3 is de-energized, it connects to
the modulator IF input at J32 and from
there to the rest of the board. At this
point, the Modulator Enable LED DS5
will be lit.
4.3.7.2 Receiver Selected
With the receiver selected, J11-10 and
J11-28, which are on the rear of the
UHF exciter tray and connect to J30 on
the board, are not connected together;
relays K3 and K4 are energized. When
K4 is energized, it connects the
receiver IF input at J1, if present, to
the rest of the board. When K3 is
energized, it connects to the modulator
IF input at J32 to 50 watts. At this
point, the Modulator Enable LED DS5
will not be lit.
4.3.7.3 Main IF Signal Path (Part 1 of 3)
The selected visual + aural IF input (0
dBm) signal is split, with one half
entering a bandpass filter consisting of
L3, L4, C4, L5, and L6. This bandpass
filter, which can be tuned with C4, is
substantially broader than the IF signal
bandwidth. It is used to slightly steer
the frequency response of the IF and
make up for any small discrepancies in
the frequency response in the stages
that precede this point. The filter also
serves the additional function of
rejecting unwanted frequencies that
may occur if the tray cover is off and
the tray is in a high RF environment.
This allows for the servicing of this
transmitter with the tray cover off in
spite of being in the presence of other
RF signals. The filtered IF signal is fed
through a pi-type matching pad,
consisting of R2, R3, and R4, to the
pin-diode attenuator circuit consisting
of CR1, CR2, and CR3.
4.3.7.4 Input Level Detector Circuit
The other part of the split IF input is
connected through L2 and C44 to U7,
an IC amplifier, which is the input to
the input level detector circuit. The
amplified IF is fed to T4, a step-up
transformer, that feeds diode detector
CR14. The positive-going detected
signal is then low-pass filtered by C49,
L18, and C50; this allows only the
video with positive sync to be applied
through emitter follower Q1. The signal
is then connected to detector CR15,
which produces a peak-sync voltage
that is applied to op-amp U9A. There is
a test point at TP3 that provides a
voltage reference check of the input
level. The detector serves the dual
function of providing a reference that
determines the input IF signal level to
the board and acting as an input
threshold detector.
The input threshold detector prevents
the automatic level control from
reducing the attenuation of the pin-
diode attenuator to minimum
(maximum signal) if the IF input to the
board is removed. The ALC, video loss
cutback, and the threshold detector
circuits will only operate when jumper
W3 on jack J6 is in the Auto position,
between pins 1 and 2. Without the
threshold detector, with the pin-diode
attenuator at minimum when the signal
is restored, the stages following this
board will be overdriven.
On the threshold detector, the
minimum IF input level at TP3 is fed
through detector CR15 to op-amp IC
U9A, pin 2. The reference voltage for
the op-amp is determined by the
voltage divider consisting of R50 and
R51 off of the +12 VDC line. When the
detected input signal level at U9A, pin
2, falls below this reference threshold,
approximately 10 dB below the normal
input level, the output of U9A, pin 1,
goes to the +12 VDC rail. This high is
connected to the base of Q2, which is
forward biased, and creates a current