Product data

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 19 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
TDO/SWO 1 A1 A1
[1][7]
O TDO — Test Data out for JTAG interface.
O SWO — Serial wire trace output.
TDI 2 C3 C4
[1][8]
I TDI — Test Data in for JTAG interface.
TMS/SWDIO 3 B1 B3
[1][8]
I TMS — Test Mode Select for JTAG interface.
I/O SWDIO — Serial wire debug data input/output.
TRST
4C2A2
[1][8]
I TRST — Test Reset for JTAG interface.
TCK/SWDCLK 5 C1 D4
[1][7]
I TCK — Test Clock for JTAG interface.
I SWDCLK — Serial wire clock.
RTCK 100 B2 B2
[1][7]
O RTCK — JTAG interface control signal.
RSTOUT
14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the
microcontroller being in Reset state.
RESET
17 F3 C6
[9]
I External reset input: A LOW-going pulse as short as 50 ns on this
pin resets the device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin at address 0.
TTL with hysteresis, 5 V tolerant.
XTAL1 22 H2 D7
[10][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 23 G3 A9
[10][11]
O Output from the oscillator amplifier.
RTCX1 16 F2 A7
[10][11]
I Input to the RTC oscillator circuit.
RTCX2 18 G1 B7
[10]
O Output from the RTC oscillator circuit.
V
SS
31,
41,
55,
72,
83,
97
B3,
B7,
C9,
G7,
J6,
K3
E5,
F5,
F6,
G5,
G6,
G7
[10]
I ground: 0 V reference.
V
SSA
11 E1 B5
[10]
I analog ground: 0 V reference. This should nominally be the same
voltage as V
SS
, but should be isolated to minimize noise and error.
V
DD(3V3)
28,
54,
71,
96
K2,
H9,
C10
, A3
E4,
E6,
F7,
G4
[10]
I 3.3 V supply voltage: This is the power supply voltage for the I/O
ports.
V
DD(REG)(3V3)
42,
84
H6,
A7
F4,
F0
[10]
I 3.3 V voltage regulator supply voltage: This is the supply voltage
for the on-chip voltage regulator only.
V
DDA
10 E2 A4
[10]
I analog 3.3 V pad supply voltage: This should be nominally the
same voltage as V
DD(3V3)
but should be isolated to minimize noise
and error. This voltage is used to power the ADC and DAC. This pin
should be tied to 3.3 V if the ADC and DAC are not used.
VREFP 12 E3 A5
[10]
I ADC positive reference voltage: This should be nominally the
same voltage as V
DDA
but should be isolated to minimize noise and
error. Level on this pin is used as a reference for ADC and DAC.
This pin should be tied to 3.3 V if the ADC and DAC are not used.
Table 5. Pin description
…continued
Symbol Pin/ball Type Description
LQFP100 TFBGA100 WLCSP100