Product data

LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 64 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
12.9 SPI
[1] T
SPICYC
= (T
cy(PCLK)
 n)  0.5 %, n is the SPI clock divider value (n  8); PCLK is derived from the
processor clock CCLK.
[2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %)
edge of the data signal (MOSI or MISO).
Table 18. Dynamic characteristics of SPI pins
T
amb
=  40  C to +85  C.
Symbol Parameter Min Typ Max Unit
T
cy(PCLK)
PCLK cycle time 10 - - ns
T
SPICYC
SPI cycle time
[1]
79.6 - - ns
t
SPICLKH
SPICLK HIGH time 0.485  T
SPICYC
-- ns
t
SPICLKL
SPICLK LOW time - 0.515  T
SPICYC
ns
SPI master
t
SPIDSU
SPI data set-up time
[2]
0--ns
t
SPIDH
SPI data hold time
[2]
2  T
cy(PCLK)
 5 - - ns
t
SPIQV
SPI data output valid time
[2]
2  T
cy(PCLK)
+ 30 - - ns
t
SPIOH
SPI output data hold time
[2]
2  T
cy(PCLK)
+ 5 - - ns
SPI slave
t
SPIDSU
SPI data set-up time
[2]
0--ns
t
SPIDH
SPI data hold time
[2]
2  T
cy(PCLK)
+ 5 - - ns
t
SPIQV
SPI data output valid time
[2]
2  T
cy(PCLK)
+ 35 - - ns
t
SPIOH
SPI output data hold time
[2]
2  T
cy(PCLK)
+ 15 - - ns
Fig 24. SPI master timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad986
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID DATA VALID
t
SPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID