Product data
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 66 of 89
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
13. ADC electrical characteristics
[1] V
DDA
and VREFP should be tied to V
DD(3V3)
if the ADC and DAC are not used.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 28.
[4] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 28
.
[5] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 28
.
[6] ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360.
[7] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 28
.
[8] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 28
.
[9] See Figure 29
.
[10] The conversion frequency corresponds to the number of samples per second.
Fig 27. SPI slave timing (CPHA = 0)
SCK (CPOL = 0)
MOSI
MISO
002aad989
T
SPICYC
t
SPICLKH
t
SPICLKL
t
SPIDSU
t
SPIDH
t
SPIQV
DATA VALID DATA VALID
t
SPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID
Table 19. ADC characteristics (full resolution)
V
DDA
= 2.5 V to 3.6 V; T
amb
=
40
C to +85
C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.
[1]
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DDA
V
C
ia
analog input capacitance - - 15 pF
E
D
differential linearity error
[2][3]
--1LSB
E
L(adj)
integral non-linearity
[4]
--3LSB
E
O
offset error
[5][6]
--2LSB
E
G
gain error
[7]
--0.5%
E
T
absolute error
[8]
--4LSB
R
vsi
voltage source interface
resistance
[9]
--7.5k
f
clk(ADC)
ADC clock frequency - - 13 MHz
f
c(ADC)
ADC conversion frequency
[10]
--200kHz