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SX1272/73

www.semtech.comPage 1

WIRELESS, SENSING & TIMING DATASHEET

SX1272/73 - 860 MHz to 1020 MHz Low Power Long Range Transceiver

Rev. 2 - July 2014

The SX1272/73 transceivers feature the LoRa

long range

modem that provides ultra-long range spread spectrum

communication and high interference immunity whilst

minimising current consumption.

Using Semtech’s patented LoRa

modulation technique

SX1272/73 can achieve a sensitivity of over -137 dBm using

a low cost crystal and bill of materials. The high sensitivity

combined with the integrated +20 dBm power amplifier

yields industry leading link budget making it optimal for any

application requiring range or robustness. LoRa

also

provides significant advantages in both blocking and

selectivity over conventional modulation techniques, solving

the traditional design compromise between range,

interference immunity and energy consumption.

These devices also support high performance (G)FSK

modes for systems including WMBus, IEEE802.15.4g. The

SX1272/73 deliver exceptional phase noise, selectivity,

receiver linearity and IIP3 for significantly lower current

consumption than competing devices.

 QFN 28 Package - Operating Range from -40 to +85°C

 Pb-free, Halogen free, RoHS/WEEE compliant product

 LoRa

Modem

 157 dB maximum link budget

 +20 dBm at 100 mW constant RF output vs. V supply

 +14 dBm high efficiency PA

 Programmable bit rate up to 300 kbps

 High sensitivity: down to -137 dBm

 Bullet-proof front end: IIP3 = -12.5 dBm

 89 dB blocking immunity

 Low RX current of 10 mA, 100 nA register retention

 Fully integrated synthesizer with a resolution of 61 Hz

 FSK, GFSK, MSK, GMSK, LoRa

and OOK modulation

 Built-in bit synchronizer for clock recovery

 Preamble detection

 127 dB Dynamic Range RSSI

 Automatic RF Sense and CAD with ultra-fast AFC

 Packet engine up to 256 bytes with CRC

 Built-in temperature sensor and low battery indicator

 Automated Meter Reading

 Home and Building Automation

 Wireless Alarm and Security Systems

 Industrial Monitoring and Control

 Long range Irrigation Systems

GENERAL DESCRIPTION

ORDERING INFORMATION

Part Number Delivery MOQ / Multiple

SX1272IMLTRT T&R 3000 pieces

SX1273IMLTRT T&R 3000 pieces

KEY PRODUCT FEATURES

APPLICATIONS

Summary of content (129 pages)

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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET SX1272/73 - 860 MHz to 1020 MHz Low Power Long Range Transceiver GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1272/73 transceivers feature the LoRaTM long range modem that provides ultra-long range spread spectrum communication and high interference immunity whilst minimising current consumption. Using Semtech’s patented LoRaTM modulation technique SX1272/73 can achieve a sensitivity of over -137 dBm using a low cost crystal and bill of materials.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page 1. General Description ............................................................................................................................................... 10 1.1. Simplified Block Diagram ............................................................................................................................... 10 1.2. Product Versions ...........................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page 4.1.6.1. Digital IO Pin Mapping ...................................................................................................................... 42 4.2. FSK/OOK Modem .......................................................................................................................................... 43 4.2.1. Bit Rate Setting ..........................................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page 4.2.12. Digital IO Pins Mapping ...........................................................................................................................65 4.2.13. Continuous Mode ....................................................................................................................................66 4.2.13.1. General Description ..................................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page 7.1. Crystal Resonator Specification................................................................................................................... 114 7.2. Reset of the Chip ......................................................................................................................................... 114 7.2.1. POR..................................................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page Table 1. SX1272/73 Device Variants and Key Parameters ...........................................................................................11 Table 2. Pin Description ................................................................................................................................................12 Table 3. Absolute Maximum Ratings ...........................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page Table 40. Register Map .................................................................................................................................................93 Table 41. Register Map, LoRa Mode ...........................................................................................................................107 Table 42. Crystal Specification .................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page Figure 1. SX1272/73 Block Diagram ............................................................................................................................10 Figure 2. Pin Diagram ...................................................................................................................................................11 Figure 3. Package Marking ......................................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table of contents Section Page Figure 40. TCXO Connection .......................................................................................................................................78 Figure 41. Typical Phase Noise Performances of the Low Consumption and Low Phase Noise PLLs. ......................80 Figure 42. RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 1. General Description The SX1272/73 incorporates the LoRaTM spread spectrum modem which is capable of achieving significantly longer range than existing systems based on FSK or OOK modulation. With this new modulation scheme sensitivities 8 dB better than equivalent data rate FSK can be achieved with a low-cost, low-tolerance crystal reference.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 1.2. Product Versions The features of the two product variants SX1272 and SX1273 are detailed in the following table. Table 1 SX1272/73 Device Variants and Key Parameters Part Number Frequency Range SX1272 SX1273 LoRaTM Parameters Spreading Factor Bandwidth Effective Bitrate Sensitivity 860 - 1020 MHz 6 - 12 125 - 500 kHz 0.24 - 37.5 kbps -117 to -137 dBm 860 - 1020 MHz 6-9 125 - 500 kHz 1.7 - 37.5 kbps -117 to -130 dBm 1.3.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 1.4.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 1.5. Package Marking Figure 3. Package Marking Rev. 2 - July 2014 ©2014 Semtech Corporation Page 13 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 2. Electrical Characteristics 2.1. ESD Notice The SX1272/73 is a high performance radio frequency device. It satisfies:   Class II of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins. Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins It should thus be handled with all the necessary ESD precautions to avoid any permanent damage. 2.2.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 2.5. Chip Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1 = VBAT2 = VDD = 3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, Pout = +13 dBm, 2 level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kbps and terminated in a matched 50 Ohm impedance, unless otherwise specified. Shared Rx and Tx path matching.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET BRF Bit rate, FSK Programmable values (1) 1.2 - 300 kbps BRO Bit rate, OOK Programmable 1.2 - 32.768 kbps BRA Bit Rate Accuracy ABS(wanted BR - available BR) - - 250 ppm FDA Frequency deviation, FSK (1) Programmable FDA + BRF/2 =< 250 kHz 0.6 - 200 kHz Note For Maximum Bit Rate the maximum modulation index is 0.5. 2.5.3.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET IIP2 2nd Order input intercept point unwanted tones are 20 MHz above the LO IIP3 3rd Order input intercept point unwanted tones are 1 MHz and 1.995 MHz above the LO BW_SSB Single Side channel filter BW Programmable IMR Image Rejection Wanted signal power sensitivity +3 dB BER = 0.1% IMA Image Attenuation DR_RSSI RSSI Dynamic Range Highest LNA gain - +57 - dBm Highest LNA gain G1 LNA gain G2, 4dB sensitivity reduction. - -12.5 -8.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET ACP Transmitter adjacent channel power (measured at 25 kHz offset) BT = 1. Measurement conditions as defined by EN 300 220-1 V2.3.1 - - -37 TS_TR Transmitter wake up time, to the first rising edge of DCLK Frequency Synthesizer enabled, PaRamp = 10 us, BR = 4.8 kbps - 120 - dBm us 2.5.5. Electrical specification for LoRaTM modulation The table below gives the electrical specifications for the transceiver operating with LoraTM modulation.
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SX1272/73 WIRELESS, SENSING & TIMING Symbol DATASHEET Description Conditions Min. Typ Max Unit - 57 - dBm 0.24 - 37.5 2nd order input intercept point, highest LNA gain, FRF = 868 MHz, CW interferer.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 2.5.6. Digital Specification Conditions: Temp = 25° C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified. Table 11 Digital Specification Symbol Description Conditions Min Typ Max Unit VIH Digital input level high 0.8 - - VDD VIL Digital input level low - - 0.2 VDD VOH Digital output level high Imax = 1 mA 0.9 - - VDD VOL Digital output level low Imax = -1 mA - - 0.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 3. SX1272/73 Features This section gives a high-level overview of the functionality of the SX1272/73 low-power, highly integrated transceiver. The following figure shows a simplified block diagram of the SX1272/73. Figure 4. Simplified SX1272 Block Schematic Diagram SX1272/73 Is a half-duplex, low-IF transceiver. Here the received RF signal is first amplified by the LNA. The LNA input is single ended to minimize the external BoM and for ease of design.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The SX1272/73 are equipped with both standard FSK and long range spread spectrum (LoRaTM) modems. Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRaTM spread spectrum modem. 3.1. LoRaTM Modem The LoRaTM modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy modulation techniques, permits an increase in link budget and increased immunity to in-band interference.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4. SX1272/73 Digital Electronics 4.1. The LoRaTM Modem The LoRaTM modem uses spread spectrum modulation and forward error correction techniques to increase the range and robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the performance improvement possible for several settings are summarised in the table below.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.1. Link Design Using the LoRaTM Modem 4.1.1.1. Overview The LoRaTM modem is setup as shown in the following figure. This configuration permits the simple replacement of the FSK modem with the LoRaTM modem via the configuration register setting RegOpMode. This change can be performed on the fly (in Sleep operating mode) thus permitting the use of both standard FSK or OOK in conjunction with the long range capability.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.1.2. Spreading Factor The spread spectrum LoRaTM modulation is performed by representing each bit of payload information by multiple chips of information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can optionally be included in the packet header for use by the receiver. Please consult Section 4.1.1.6 for more information on the LoRaTM packet and header. 4.1.1.4.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.1.6. LoRaTM Packet Structure The LoRaTM modem employs two types of packet format, explicit and implicit. The explicit packet includes a short header that contains information about the number of bytes, coding rate and whether a CRC is used in the packet. The packet format is shown in the following figure. The LoRaTM packet comprises three elements:    A preamble. An optional header. The data payload. Figure 6.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to discard invalid headers. In Explicit Header Mode the presence of the payload CRC selected on the transmit side through the use of the bit RxPayloadCrcOn locatind in the register RegModemConfig1. The corresponding bit (RxPayloadCrcOn) is hence unused on the receive side.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Payload The packet payload is a variable-length field that contains the actual data coded at the error rate either as specified in the header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. For more information on the payload and how it is loaded from the data buffer FIFO please see Section 4.1.2.3. 4.1.1.7.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Principle of Operation The principle behind the FHSS scheme is that a portion of each LoRaTM packet is transmitted on each hopping channel from a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the transmitter and receiver change to the next channel in a predefined list of hopping frequencies to continue transmission and reception of the next portion of the packet.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.2. LoRaTM Digital Interface The LoRaTM modem comprises three types of digital interface, static configuration registers, status registers and a FIFO data buffer. All are accessed through the SX1272/73’s SPI interface - full details of each type of register are given below. Full listings of the register addresses used for SPI access are given in Section 6.3. 4.1.2.1.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Principle of Operation Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO data buffer. The register RegFifoTxBaseAddr specifies the point in memory where the transmit information is stored. Similarly, for receiver operation, the register RegFifoRxBaseAddr indicates the point in the data buffer where information will be written to in event of a receive operation.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.3. Operation of the LoRaTM Modem 4.1.3.1. Operating Mode Control The operating modes of the LoRaTM modem are accessed by enabling LoRaTM mode (setting the LongRangeMode bit of RegOpMode). Depending upon the operating mode selected the range of functionality and register access is given by the following table: Table 15 LoRaTM Operating Mode Functionality Operating Mode Description SLEEP Low-power mode.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.4. Frequency Settings Recalling that the frequency step is given by: F XOSC F STEP = --------------19 2 In order to set LO frequency values following registers are available. Frf is a 24-bit register which defines carrier frequency. The carrier frequency relates to the register contents by following formula: F RF = F STEP × Frf (23,0) 4.1.5.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.1.6. LoRaTM Modem State Machine Sequences The sequence for transmission and reception of data to and from the LoRaTM modem, together with flow charts of typical sequences of operation, are detailed below. Data Transmission Sequence In transmit mode power consumption is optimized by enabling RF, PLL and PA blocks only when packet data needs to be transmitted. Figure 10 shows a typical LoRaTM transmit sequence. Figure 10.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET LoRaTM Transmit Data FIFO Filling In order to write packet data into FIFO user should: 1 Set FifoAddrPtr to FifoTxBaseAddrs. 2 Write PayloadLength bytes to the FIFO (RegFifo) Data Reception Sequence Figure 11 shows typical LoRaTM receive sequences for both single and continuous receiver modes of operation. Figure 11. LoRaTM receive sequence. Rev. 2 - July 2014 ©2014 Semtech Corporation Page 36 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The LoRaTM modem can work in two distinct reception modes: 1. Single receive mode 2. Continuous receive mode Single Reception Operating Mode In this mode, the modem searches for a preamble during a given time window. If a preamble hasn’t been found at the end of the time window, the chip generates the RxTimeout interrupt and goes back to stand-by mode.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET In continuous mode the received packet processing sequence is given below. 1 Whilst in Sleep or Stand-by mode select RXCONT mode. 2 Upon reception of a valid header CRC the RxDone interrupt is set. The radio remains in RXCONT mode waiting for the next RX LoRaTM packet. 3 The PayloadCrcError flag should be checked for packet integrity. 4 If packet has been correctly received the FIFO data buffer can be read (see below).
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The software packet filtering process follows the steps below:  Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable, this variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the SX1272 gives in real time the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be written by the receive LoRaTM modem).
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Channel activity detection The use of a spread spectrum modulation technique presents challenges in determining whether the channel is already in use by a signal that may be below the noise floor of the receiver. The use of the RSSI in this situation would clearly be impracticable. To this end the channel activity detector is used to detect the presence of other LoRaTM signals. Figure 12 shows the channel activity detection (CAD) process: Figure 12.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Principle of Operation The channel activity detection mode is designed to detect a LoRa preamble on the radio channel with the best possible power efficiency. Once in CAD mode, the SX1272/73 will perform a very quick scan of the band to detect a LoRaTM packet preamble. During a CAD the following operations take place:   The PLL locks The radio receiver captures LoRaTM preamble symbol of data from the channel.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET To illustrate this process and the respective consumption in each mode, the CAD process follows the sequence of events outlined below: Figure 14. Consumption Profile of the LoRa CAD Process The receiver is then in full receiver mode for just over half of the activity detection, followed by a reduced consumption processing phase where the consumption varies with the LoRa bandwidth as shown in the table below.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2. FSK/OOK Modem 4.2.1. Bit Rate Setting The bit rate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently chip) rate of the radio. In continuous transmit mode (Section 4.2.
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SX1272/73 WIRELESS, SENSING & TIMING Type Round bit rates (multiples of 12.5, 25 and 50 kbps) Watch Xtal frequency DATASHEET BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) 0x0A 0x00 12.5 kbps 12.5 kbps 12500.00 0x05 0x00 25 kbps 25 kbps 25000.00 0x80 0x00 50 kbps 50000.00 0x01 0x40 100 kbps 100000.0 0x00 0xD5 150 kbps 150234.7 0x00 0xA0 200 kbps 200000.0 0x00 0x80 250 kbps 250000.0 0x00 0x6B 300 kbps 299065.4 0x03 0xD1 32.768 kbps 32.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Note The transmitter must be restarted if the ModulationShaping setting is changed in order to recalibrate the built-in filter. 4.2.3. FSK/OOK Reception 4.2.3.1. FSK Demodulator The FSK demodulator of the SX1272/73 is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index (β) of the signal is greater than 0.5 and below 10: 2 × F DEV 0.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden received signal power reduction is possible, the three parameters should be optimized accordingly. Optimizing the Floor Threshold OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor).
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:   Fixed Threshold: The value is selected through OokFixedThresh Average Threshold: Data supplied by the RSSI block is averaged (this operation mode should only be used with DCfree encoded data). 4.2.3.3.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.3.4. Frequency Error Indicator This frequency error indicator measures the frequency error between the programmed RF centre frequency and the carrier frequency of the modulated input signal to the receiver. When the FEI is performed the frequency error is measured and the signed result is loaded in FeiValue in RegFei in 2’s complement format. The time required for an FEI evaluation is 4 bit periods.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.3.6. Preamble Detector The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3 bytes with PreambleDetectorSize in RegPreambleDetect as defined in the next table.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The calibration process takes approximately 10 ms. 4.2.3.9. Timeout Function The SX1272/73 includes a Timeout function, which allows the automation of a duty-cycled recceive oprtation where the radio periodically wakes from sleep mode into receiver mode.  Timeout interrupt is generated TimeoutRxRssi x 16 x Tbit after switching to Rx mode if the Rssi flag does not raise within this time frame (RssiValue > RssiThreshold).
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.6. Startup Times The startup time of the transmitter or the receiver is dependent upon which mode the transceiver was in at the beginning. For a complete description, Figure 18 below shows a complete startup process, from the lower power mode “Sleep”. Current Drain IDDR (Rx) or IDDT (Tx) IDDFS IDDST IDDSL 0 Timeline TS_OSC TS_OSC +TS_FS TS_OSC +TS_FS +TS_TR FSTx Sleep mode TS_OSC +TS_FS +TS_RE Transmit Stdby mode FSRx Receive Figure 18.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table 22 Receiver Startup Time Summary RxBw if AfcAutoOn=0 RxBwAfc if AfcAutoOn=1 2.6 kHz 3.1 kHz 3.9 kHz 5.2 kHz 6.3 kHz 7.8 kHz 10.4 kHz 12.5 kHz 15.6 kHz 20.8 kHz 25.0 kHz 31.3 kHz 41.7 kHz 50.0 kHz 62.5 kHz 83.3 kHz 100.0 kHz 125.0 kHz 166.7 kHz 200.0 kHz 250.0 kHz TS_RE (+/-5%) 2.33 ms 1.94 ms 1.56 ms 1.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.6.4. Tx to Rx Turnaround Time Timeline 0 TS_HOP +TS_RE Tx Mode 1. set new Frf (*) 2. set Rx mode Rx Mode (*) Optional Figure 20. Tx to Rx Turnaround Note The SPI instruction times are omitted, as they can generally be very small as compared to other timings (up to 10 MHz SPI clock). 4.2.6.5. Rx to Tx Timeline 0 TS_HOP +TS_TR Rx Mode 1. set new Frf (*) 2. set Tx mode Tx Mode (*) Optional Figure 21. Rx to Tx Turnaround Rev.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.6.6. Receiver Hopping, Rx to Rx Two methods are possible: First method Timeline 0 TS_HOP +TS_RE Rx Mode, Channel A Rx Mode, Channel B 1. set new Frf 2. set RestartRxWithPllLock Second method Timeline 0 ~TS_HOP Rx Mode, Channel A 1. set FastHopOn=1 2. set new Frf (*) 3. wait for TS_HOP Rx Mode, Channel B (*) RegFrfLsb must be written to trigger a frequency change Figure 22.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Automatic restart capabilities are detailed in Section 4.2.8. The receiver startup options available in SX1272/73 are described in Table 23.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.8.3. Automatic Restart when Packet Collision is Detected In receive mode the SX1272/73 is able to detect packet collision and restart the receiver. Collisions are detected by a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network configurations where many asynchronous slaves attempt periodic communication with a single a master node.
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SX1272/73 WIRELESS, SENSING & TIMING RxTimeout DATASHEET Defines the action to be taken on a RxTimeout interrupt. RxTimeout interrupt can be a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt. 4.2.9.2. Sequencer Transitions The transitions between sequencer states are listed in the forthcoming table.
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SX1272/73 WIRELESS, SENSING & TIMING FromPacketReceived DATASHEET Controls the state-machine transition from the PacketReceived state: 000: to SequencerOff state 001: to Transmit on a FifoEmpty interrupt 010: to LowPowerSelection 011: to Receive via FS mode, if frequency was changed 100: to Receive state (no frequency change) 4.2.9.3. Timers Two timers (Timer1 and Timer2) are also available in order to define periodic sequences.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table 26 Sequencer Timer Settings Variable Description Timer1Resolution Resolution of Timer1 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Timer2Resolution Resolution of Timer2 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Timer1Coefficient Multiplying coefficient for Timer1 Timer2Coefficient Multiplying coefficient for Timer2 Rev. 2 - July 2014 ©2014 Semtech Corporation Page 59 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.9.4. Sequencer State Machine The following graphs summarize every possible transition between each Sequencer state. The Sequencer states are highlighted in grey. The transitions are represented by arrows. The condition activating them is described over the transition arrow. For better readability, the start transitions are separated from the rest of the graph. Transitory states are highlighted in light grey, and exit states are represented in red.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.10. Data Processing in FSK/OOK Mode 4.2.10.1. Block Diagram Figure below illustrates the SX1272/73 data processing circuit. Its role is to interface the data to/from the modulator/ demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 Tx/Rx CONTROL Data Rx SYNC RECOG.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.11. FIFO Overview and Shift Register (SR) In packet mode of operation both data to be transmitted and that has been received are stored in a configurable FIFO (First In First Out). It is accessed via the SPI interface and provides several interrupts for transfer management. The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET FifoLevel 1 0 B B+1 # of bytes in FIFO Figure 28. FifoLevel IRQ Source Behavior Notes - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be dynamically updated by only changing the FifoThreshold parameter - FifoLevel interrupt is valid as long as FifoFull does not occur.
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SX1272/73 WIRELESS, SENSING & TIMING Rx DATA Bit N-x = (NRZ) Sync_value[x] DATASHEET Bit N-1 = Bit N = Sync_value[1] Sync_value[0] DCLK SyncAddressMatch Figure 29. Sync Word Recognition During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.12. Digital IO Pins Mapping Six general purpose IO pins are available on the SX1272/73 and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.13. Continuous Mode 4.2.13.1. General Description As illustrated in Figure 30 in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive. DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 Tx/Rx CONTROL Data Rx SYNC RECOG. SPI NSS SCK MOSI MISO Figure 30. Continuous Mode Conceptual View 4.2.13.2.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.13.3. Rx Processing If the bit synchronizer is disabled the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA Is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below. DATA (NRZ) DCLK Figure 32.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 CONTROL Data Rx SYNC RECOG. PACKET HANDLER FIFO (+SR) SPI NSS SCK MOSI MISO Tx Figure 33. Packet Mode Conceptual View Note The Bit Synchronizer is automatically enabled in Packet mode. 4.2.14.2. Packet Format Fixed Length Packet Format Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Optional DC free data coding CRC checksum calculation Preamble Sync Word 0 to 65536 bytes 0 to 8 bytes Address byte Message Up to 2047 bytes CRC 2-bytes Payload (min 1 byte) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 34.
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SX1272/73 WIRELESS, SENSING & TIMING  DATASHEET Optional 2-bytes CRC checksum Optional DC free data coding CRC checksum calculation Preamble Sync Word 0 to 65536 bytes 0 to 8 bytes Length byte Address byte Message Up to 255 bytes CRC 2-bytes Payload (min 2 bytes) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 35.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.14.3. Tx Processing In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload available in the FIFO:    Add a programmable number of preamble bytes.  Optional DC-free encoding of the data (Manchester or whitening). Add a programmable Sync word. Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and appending the 2 bytes checksum.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails. 4.2.14.5.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Address Based Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering above Sync word (i.e. Sync must match first) and is typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available:  AddressFiltering = 01: Received address field is compared with internal register NodeAddress.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.2.14.7. DC-Free Data Mechanisms The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random and DC free.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET L F S R P o ly n o m ia l = X 9 + X 5 + 1 X8 X7 X6 X5 X4 X3 T ran sm it d ata X2 X1 X0 W hite ne d d ata Figure 38. Data Whitening Polynomial 4.2.14.8. Beacon Tx Mode In some short range wireless network topologies a repetitive message, also known as beacon, is transmitted periodically by a transmitter. The Beacon Tx mode allows for the re-transmission of the same packet without having to fill the FIFO multiple times with the same data.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 4.3. SPI Interface The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Three access modes to the registers are provided:  SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is therefore a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. Rev. 2 - July 2014 ©2014 Semtech Corporation Page 77 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 5. SX1272/73 Analog & RF Frontend Electronics 5.1. Power Supply Strategy The SX1272/73 employs an internal voltage regulation scheme which provides stable operating voltage, and hence device characteristics, over the full industrial temperature and operating voltage range. This includes up to +17 dBm of RF output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 5.3.2. CLKOUT Output The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2. Two typical applications of the CLKOUT output include:  To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Figure 41. Typical Phase Noise Performances of the Low Consumption and Low Phase Noise PLLs. Note In receive mode only the low consumption PLL is available. The SX1272/73 PLL uses a 19-bit sigma-delta modulator whose frequency resolution, constant over the whole frequency range, is given by: F XOSC F STEP = --------------19 2 Rev. 2 - July 2014 ©2014 Semtech Corporation Page 80 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET The carrier frequency is programmed through RegFrf, split across addresses 0x06 to 0x08: F RF = F STEP × Frf (23,0) Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows the potential for user generation of m-ary FSK at very low bit rates.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 5.4. Transmitter Description The transmitter of SX1272/73 comprises the frequency synthesizer, modulator (both LoRaTM and FSK/OOK) and power amplifier blocks, together with the DC biasing and ramping functionality that is provided through the VR_PA block. 5.4.1. Architecture Description The architecture of the RF front end is shown in the following diagram.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Notes - For +20 dBm restrictions on operation please consult the following section. - To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to permit delivery of the requisite supply current. - If the PA_BOOST pin is not used it may be left floating. 5.4.3.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 5.4.4. Over Current Protection The power amplifiers of SX1272/73 are protected against current over supply in adverse RF load conditions by the over current protection block. This has the added benefit of protecting battery chemistries with limited peak current capability and minimising worst case PA consumption in battery life calculations.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Figure 43. Receiver Block Diagram 5.5.3. Automatic Gain Control In FSK/OOK Mode The AGC feature allows receiver to handle a wide Rx input dynamic range from the sensitivity level up to maximum input level of 0 dBm or more, whilst optimizing the system linearity. The following table shows typical NF and IIP3 performances for the SX1272/73 LNA gains available.
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SX1272/73 DATASHEET G1 G2 AgcStep3 Ag c  AgcStep4 AgcStep5 G4 G5 G3 Th re sh 5 hr es Ag cT    AgcStep2 h4 h3 Ag cT cT h Ag Ag  AgcStep1 hr es h2 re s h1 re s cT h C AG  Towards -125 dBm Re fe re nc e WIRELESS, SENSING & TIMING Higher Sensitivity Lower Linearity Lower Noise Figure Pin [dBm] G6 Lower Sensitivity Higher Linearity Higher Noise Figure Figure 44.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Table 37 RssiSmoothing Options RssiSmoothing ‘000’ ‘001’ ‘010’ ‘011’ ‘100’ ‘101’ ‘110’ ‘111’ Number of Samples 2 4 8 16 32 64 128 256 Estimated Accuracy ± 6 dB ± 5 dB ± 4 dB ± 3 dB ± 2 dB ± 1.5 dB ± 1.2 dB ± 1.1 dB Response Time 2 (RssiSmoothing +1) [ms] 4 ⋅ RxBw[kHz ] The RSSI is calibrated when the image and RSSI calibration process is launched. Please see Section Table 4.2.3.8 for details. 5.5.5.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 5.5.6. Channel Filter The role of the channel filter is to reject noise and interference outside of the wanted channel. The SX1272/73 channel filtering is implemented with a 16-tap finite impulse response (FIR) filter. Rejection of the filter is high enough that the filter stop-band performance is not the dominant influence on adjacent channel rejection performance. This is instead limited by the SX1272/73 PLL phase noise.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Due to process variations the absolute accuracy of the result is +/- 10 °C. Higher precision requires a calibration procedure at a known temperature. The figure below shows the influence of just such a calibration process. For more information, including source code, please consult the applications section of this document. Figure 45. Temperature Sensor Response Rev. 2 - July 2014 ©2014 Semtech Corporation Page 89 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 6. Description of the Registers The register mapping depends upon whether FSK/OOK or LoRaTM mode has been selected. The following table summarises the location and function of each register and gives an overview of the changes in register mapping between both modes of operation. 6.1.
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SX1272/73 WIRELESS, SENSING & TIMING Address 0x1B 0x1C 0x1D Register Name FSK/OOK Mode LoRaTM Mode RegAfcMsb RegAfcLsb RegFeiMsb RegRssiValue RegHopChannel RegModemConfig 1 DATASHEET Reset (POR) Default (FSK) 0x00 0x00 0x00 n/a n/a RegFeiLsb RegModemConfig 2 0x00 n/a 0x1F RegPreambleDetect 0x40 0xAA 0x20 0x21 RegRxTimeout1 RegRxTimeout2 RegSymbTimeout Lsb RegPreambleMsb RegPreambleLsb 0x22 RegRxTimeout3 RegPayloadLength 0x00 0x23 RegRxDelay 0x00 0x24 RegOsc RegMaxPayloadL engt
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SX1272/73 WIRELESS, SENSING & TIMING Address Register Name FSK/OOK Mode 0x38 0x39 0x3A 0x3B RegTimerResol RegTimer1Coef RegTimer2Coef RegImageCal 0x3C 0x3D 0x3E RegTemp RegLowBat RegIrqFlags1 0x3F RegIrqFlags2 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x4B 0x58 0x5A 0x5C 0x5E 0x6C 0x70 LoRaTM Mode DATASHEET Reset (POR) Default (FSK) 0x00 0xF5 0x20 0x82 RESERVED RegDioMapping1 RegDioMapping2 RegVersion RegAgcRef RegAgcThresh1 RegAgcThresh2 RegAgcThresh3 RegPllHop RegTcxo RegPaDac RegPll RegPllLowPn R
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 6.2. FSK/OOK Mode Register Map This section details the SX1272/73 register mapping and the precise contents of each register in FSK/OOK mode.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegFdevMsb (0x04) DATASHEET Bits Variable Name Mode Default value 7-6 unused r 0x00 unused 5-0 Fdev(13:8) rw 0x00 MSB of the frequency deviation FSK/OOK Description LSB of the frequency deviation RegFdevLsb (0x05) 7-0 Fdev(7:0) rw 0x52 Fdev = Fstep × Fdev (15,0) Default value: 5 kHz RegFrfMsb (0x06) 7-0 Frf(23:16) rw 0xE4 MSB of the RF carrier frequency RegFrfMid (0x07) 7-0 Frf(15:8) rw 0xC0 MSB of the RF carrier frequenc
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) DATASHEET Bits Variable Name Mode Default value 7-6 unused r 0x00 unused 5 OcpOn rw 0x01 Enables overload current protection (OCP) for the PA: 0  OCP disabled 1  OCP enabled 0x0B Trimming of OCP current: Imax = 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) / Imax = -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to 240 mA) Imax = 240mA for higher settings Default Imax = 100mA RegOcp (0x0B) 4-0 OcpTrim rw FSK/OOK Description Registers
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) DATASHEET Bits Variable Name Mode Default value 7-3 RssiOffset rw 0x00 Signed RSSI offset, to compensate for the possible losses/gains in the front-end (LNA, SAW filter...
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Name (Address) Bits Variable Name Mode Default value RegOokFix (0x15) 7-0 OokFixedThreshold rw 0x0C Fixed threshold for the Data Slicer in OOK mode Floor threshold for the Data Slicer in OOK when Peak mode is used RegOokAvg (0x16) RegRes17 to RegRes19 RegAfcFei (0x1A) FSK/OOK Description 7-5 OokPeakThreshDec rw 0x00 Period of decrement of the RSSI threshold in the OOK demodulator: 000  once per chip 001  once every 2 chips 010  once ever
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegPreambleDetect (0x1F) Bits Variable Name DATASHEET Mode Default value Enables Preamble detector when set to 1. The AGC settings supersede this bit during the startup / AGC phase.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode Default value FSK/OOK Description 7-6 AutoRestartRxMode rw 0x02 Controls the automatic restart of the receiver after the reception of a valid packet (PayloadReady or CrcOk): 00  Off 01  On, without waiting for the PLL to re-lock 10  On, wait for the PLL to lock (frequency changed) 11  reserved 5 PreamblePolarity rw 0x00 Sets the polarity of the Preamble 0  0xAA (default) 1  0x55 4 SyncOn rw 0x01
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) DATASHEET Bits Variable Name Mode Default value 7 PacketFormat rw 0x01 Defines the packet format used: 0  Fixed length 1  Variable length FSK/OOK Description 6-5 DcFree rw 0x00 Defines DC-free encoding/decoding performed: 00  None (Off) 01  Manchester 10  Whitening 11  reserved 4 CrcOn rw 0x01 Enables CRC calculation/check (Tx/Rx): 0  Off 1  On 0x00 Defines the behavior of the packet handler when CRC check fails: 0  Clear F
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegFifoThresh (0x35) Variable Name Bits DATASHEET Mode Default value 7 TxStartCondition rw 0x01 * 6 unused r - 5-0 FifoThreshold rw 0x0f FSK/OOK Description Defines the condition to start packet transmission: 0  FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1  FifoEmpty goes low(i.e.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Variable Name Bits 7-5 FromReceive DATASHEET Mode rw Default value 0x00 FSK/OOK Description Controls the Sequencer transition from the Receive state 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPowerSelection on a PayloadReady interrupt 011: to PacketReceived state on a CrcOk interrupt (1) 100: to SequencerOff state on a Rssi interrupt 101: to SequencerOff state on a SyncAddress interrupt 110: to Sequen
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode Default value FSK/OOK Description Service registers RegImageCal (0x3B) 7 AutoImageCalOn rw 0x00 * Controls the Image calibration mechanism 0  Calibration of the receiver depending on the temperature is disabled 1  Calibration of the receiver depending on the temperature enabled. 6 ImageCalStart wt - Triggers the IQ and RSSI calibration when set in Standby mode.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegIrqFlags1 (0x3E) RegIrqFlags2 (0x3F) Bits Variable Name DATASHEET Mode Default value FSK/OOK Description 7 ModeReady r - Set when the operation mode requested in Mode, is ready - Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - Rx: RSSI sampling starts - Tx: PA ramp-up completed Cleared when changing the operating mode. 6 RxReady r - Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegDioMapping1 (0x40) RegDioMapping2 (0x41) DATASHEET Bits Variable Name Mode Default value 7-6 Dio0Mapping rw 0x00 5-4 Dio1Mapping rw 0x00 3-2 Dio2Mapping rw 0x00 1-0 Dio3Mapping rw 0x00 See Table 17 for mapping in LoRa mode 7-6 Dio4Mapping rw 0x00 5-4 Dio5Mapping rw 0x00 See Table 28 for mapping in Continuous mode See Table 29 for mapping in Packet mode 3-1 reserved rw 0x00 reserved.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) RegPll (0x5C) RegPllLowPn (0x5E) RegFormerTemp (0x6C) RegBitrateFrac (0x70) DATASHEET Bits Variable Name Mode Default value 7-6 PllBandwidth rw 0x03 Controls the PLL bandwidth: 00  75 kHz 10  225 kHz 11  300 kHz 01  150 kHz 5-0 reserved rw 0x10 reserved. Retain default value 7-6 PllBandwidth rw 0x03 Controls the Low Phase Noise PLL bandwidth: 00  75 kHz 10  225 kHz 01  150 kHz 11  300 kHz 5-0 reserved rw 0x10 reserved.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 6.3. LoRaTM Mode Register Map This section details the SX1272/73 register mapping and the precise contents of each register in LoRaTM mode. It is essential to understand that the LoRa modem is controlled independently of the FSK modem. Therefore, care should be taken when accessing the registers, especially as some register may have the same name in LoRa or FSK mode.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode LoRaTM Description Reset LSB of RF carrier frequency RegFrLsb (0x08) 7-0 Frf(7:0) rwt F(XOSC) ⋅ Frff RF = ----------------------------------19 2 0x00 Resolution is 61.035 Hz if F(XOSC) = 32 MHz. Default value is 0xe4c000 = 915 MHz. Register values must be modified only when device is in SLEEP or STAND-BY mode. register for RF RegPaConfig (0x09) 7 PaSelect rw 0x00 Selects PA output pin 0  RFIO pin.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode LoRaTM Description Reset LNA gain setting: 000  not used 001  G1 = maximum gain 010  G2 0x01 011  G3 100  G4 101  G5 110  G6 = minimum gain 111  not used 7-5 LnaGain rwx 4-2 reserved r 0x00 - 1-0 LnaBoost rw 0x00 00  Default LNA current 11  Boost on, 150% LNA current.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode Reset LoRaTM Description Timeout interrupt: writing a 1 clears the IRQ 7 RxTimeout rc 0x00 6 RxDone rc 0x00 5 PayloadCrcError rc 0x00 4 ValidHeader rc 0x00 3 TxDone rc 0x00 2 CadDone rc 0x00 1 FhssChangeChannel rc 0x00 0 CadDetected rc 0x00 Valid Lora signal detected during CAD operation: writing a 1 clears the IRQ 7-0 FifoRxBytesNb r n/a Number of payload bytes of latest packet
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Variable Name Bits DATASHEET Mode LoRaTM Description Reset RSSI of the latest packet received (dBm) RegPktRssiValue (0x1A) 7-0 PacketRssi r n/a RSSI[dBm] = - 139 + PacketRssi (when SNR >= 0) or RSSI[dBm] = - 139 + PacketRssi + PacketSnr (when SNR < 0) Current RSSI value (dBm) RegRssiValue (0x1B) RegHopChannel (0x1C) 7-0 Rssi r n/a RSSI[dBm] = - 139 + Rssi n/a PLL failed to lock while attempting a TX/RX/CAD operation 1  PLL did not loc
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode LoRaTM Description Reset 7-4 SpreadingFactor rw 0x7 SF rate (expressed as a base-2 logarithm) 6  64 chips / symbol 7  128 chips / symbol 8  256 chips / symbol 9  512 chips / symbol 10  1024 chips / symbol 11  2048 chips / symbol 12  4096 chips / symbol other values reserved.
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SX1272/73 WIRELESS, SENSING & TIMING Name (Address) Bits Variable Name DATASHEET Mode Reset LoRaTM Description RegFeiLsb (0x2A) 7-0 FreqError(7:0) r 0x0 LSB of RF Frequency Error (0x2B) - Reserved r n/a Reserved RegRssiWideband (0x2C) 7-0 RssiWideband(7:0) r n/a Wideband RSSI measurement used to locally generate a random number (0x2D) - (0x30) - Reserved r n/a Reserved 7-3 Reserved r 0xC0 Reserved 2-0 DetectionOptimize rw 0x03 LoRa detection Optimize 0x03  SF7 to SF
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7. Application Information 7.1. Crystal Resonator Specification Table 42 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1272/73. This specification covers the full range of operation of the SX1272/73 and is employed in the reference design.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.2.2. Manual Reset A manual reset of the SX1272/73 is possible even for applications in which VDD cannot be physically disconnected. Pin 6 should be pulled high for a hundred microseconds and then released. The user should then wait for 5 ms before using the chip. VDD Pin 6 (input) > 100 us Wait for 5 ms ’’1’’ High-Z High-Z Chip is ready from this point on Figure 47.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.3.1.1. Timing Diagram When no signal is received, the circuit wakes every Timer1 + Timer2 and switches to Receive mode for a time defined by Timer2, as shown on the following diagram. If no Preamble is detected, it then switches back to Idle mode, i.e. Sleep mode with RC oscillator on. No received signal Receive Idle ( Sleep + RC ) Receive Timer2 Idle Timer2 Timer1 Timer1 Timer1 Figure 49.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.3.1.2. Sequencer Configuration The following graph shows Listen mode - Wake on PreambleDetect state machine: State Machine Sequencer Off & Initial mode = Sleep or Standby IdleMode = 1 : Sleep Start bit set Start FromStart = 00 LowPower Selection LowPowerSelection = 1 Idle On T1 FromIdle = 1 On T2 Receive On PreambleDetect FromReceive = 110 Sequencer Off Figure 51.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.3.2. Wake on SyncAddress Interrupt In another possible scenario, the sequencer polls for a Preamble detection and then for a valid SyncAddress interrupt. If events occur, the sequencer is switched off and the circuit stays in Receive mode until the user switches modes. Otherwise, the receiver is switched off until the next Rx period. 7.3.2.1.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET Wanted Signal Preamble ( Preamble + Sync = T2 ) Idle Sync Word Payload Crc Receive Timer2 Timer1 RxTimeout Preamble Detect Sync Address Fifo Level Figure 54. Listen Mode with Preamble Received & Valid SyncAddress 7.3.2.2.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET LowPowerSelection FromIdle FromReceive FromRxTimeout 1: To Idle state 1: To Receive state on T1 interrupt 101: To Sequencer off on SyncAddress interrupt 10: To LowPowerSelection TTimeoutRxPreamble should be set to the expected transmit preamble duration (depends on PreambleDetectSize and BitRate). TTimer1 should be set to 64 µs (shortest possible duration). TTimer2 is set so that TTimer1 + TTimer2 defines the time between two start of reception.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.4. Top Sequencer: Beacon Mode In this mode, a single message is periodically re-transmitted. If the Payload being sent is always identical and PayloadLength is smaller than the FIFO size, the use of the BeaconOn bit in RegPacketConfig2 together with the Sequencer permit to achieve periodic beacon without any user intervention. 7.4.1.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET This example is achieved by programming the Sequencer as follows: Table 47 Beacon Mode Settings Variable IdleMode FromStart LowPowerSelection FromIdle FromTransmit Effect 1: Sleep mode 00: To LowPowerSelection 1: To Idle state 0: To Transmit state on T1 interrupt 0: To LowPowerSelection on PacketSent interrupt TTimer1 + TTimer2 define the time between the start of two transmissions. Rev. 2 - July 2014 ©2014 Semtech Corporation Page 122 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.5. Example CRC Calculation The following routine may be implemented to mimic the CRC calculation of the SX1272/73: Figure 58. Example CRC Code Rev. 2 - July 2014 ©2014 Semtech Corporation Page 123 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 7.6. Example Temperature Reading The following routine may be implemented to read the temperature and calibrate the sensor: Figure 59. Example Temperature Reading Rev. 2 - July 2014 ©2014 Semtech Corporation Page 124 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 8. Packaging Information 8.1. Package Outline Drawing The SX1272/73 is available in a 28-lead QFN package as shown in Figure 60. Figure 60. Package Outline Drawing Rev. 2 - July 2014 ©2014 Semtech Corporation Page 125 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 8.2. Recommended Land Pattern Figure 61. Recommended Land Pattern Rev. 2 - July 2014 ©2014 Semtech Corporation Page 126 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 8.3. Tape and Reel Information Figure 62. Tape and Reel Information Rev. 2 - July 2014 ©2014 Semtech Corporation Page 127 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET 9. Revision History Table 48 Revision History Revision 1 Date June 2013 2 July 2014 Rev. 2 - July 2014 ©2014 Semtech Corporation Comment First release. Inclusion of FEI Correction of ToA formula Improve description in the RSSI and IQ calibration mechanism Correction of default value in FSK Added undocumented register Page 128 www.semtech.
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SX1272/73 WIRELESS, SENSING & TIMING DATASHEET © Semtech 2014 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use.