Datasheet

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SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
RegFifoThresh
(0x35)
7 TxStartCondition rw
0x01
*
Defines the condition to start packet transmission:
0  FifoLevel (i.e. the number of bytes in the FIFO exceeds
FifoThreshold)
1  FifoEmpty goes low(i.e. at least one byte in the FIFO)
6 unused r - unused
5-0 FifoThreshold rw 0x0f
Used to trigger
FifoLevel interrupt, when:
number of bytes in FIFO >= FifoThreshold + 1
Sequencer registers
RegSeqConfig1
(0x36)
7 SequencerStart wt 0x00
Controls the top level Sequencer
When set to ‘1’, executes the “Start” transition.
The sequencer can only be enabled when the chip is in Sleep or
Standby mode.
6 SequencerStop wt 0x00
Forces the Sequencer Off.
Always reads ‘0’
5 IdleMode rw 0x00
Selects chip mode during the state:
0: Standby mode
1: Sleep mode
4-3 FromStart rw 0x00
Controls the Sequencer transition when
SequencerStart is set to 1
in Sleep or Standby mode:
00: to LowPowerSelection
01: to Receive state
10: to Transmit state
11: to Transmit state on a FifoLevel interrupt
2 LowPowerSelection rw 0x00
Selects the Sequencer LowPower state after a
to
LowPowerSelection
transition:
0: SequencerOff state with chip on Initial mode
1: Idle state with chip on
Standby or Sleep mode depending on
IdleMode
Note: Initial mode is the chip LowPower mode at
Sequencer Start.
1 FromIdle rw 0x00
Controls the Sequencer transition from the Idle state on a T1
interrupt:
0: to Transmit state
1: to Receive state
0 FromTransmit rw 0x00
Controls the Sequencer transition from the Transmit state:
0: to LowPowerSelection on a PacketSent interrupt
1: to Receive state on a
PacketSent interrupt
Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description