Datasheet

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SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
RegDioMapping1
(0x40)
7-6 Dio0Mapping rw 0x00
Mapping of pins DIO0 to DIO5
See Table 17 for mapping in LoRa mode
See Table 28 for mapping in Continuous mode
See Table 29 for mapping in Packet mode
5-4 Dio1Mapping rw 0x00
3-2 Dio2Mapping rw 0x00
1-0 Dio3Mapping rw 0x00
RegDioMapping2
(0x41)
7-6 Dio4Mapping rw 0x00
5-4 Dio5Mapping rw 0x00
3-1 reserved rw 0x00 reserved. Retain default value
0 MapPreambleDetect rw 0x00
Allows the mapping of either
Rssi Or PreambleDetect to the DIO
pins, as summarized on Table 28 and Table 29
0
 Rssi interrupt
1
 PreambleDetect interrupt
Version register
RegVersion
(0x42)
7-0 Version r 0x22
Version code of the chip. Bits 7-4 give the full revision number;
bits 3-0 give the metal mask revision number.
Additional registers
RegAgcRef
(0x43)
7-6 unused r - unused
5-0 AgcReferenceLevel rw 0x13
Sets the floor reference for all AGC thresholds:
AGC Reference [dBm] =
-174 dBm + 10*log(2*
RxBw) + SNR + AgcReferenceLevel
SNR = 8 dB, fixed value
RegAgcThresh1
(0x44)
7-5 unused r - unused
4-0 AgcStep1 rw 0x0E Defines the 1st AGC Threshold
RegAgcThresh2
(0x45)
7-4 AgcStep2 rw 0x05 Defines the 2nd AGC Threshold:
3-0 AgcStep3 rw 0x0B Defines the 3rd AGC Threshold:
RegAgcThresh3
(0x46)
7-4 AgcStep4 rw 0x0D Defines the 4th AGC Threshold:
3-0 AgcStep5 rw 0x0B Defines the 5th AGC Threshold:
RegPllHop
(0x4b)
7 FastHopOn rw 0x00
Bypasses the main state machine for a quick frequency hop.
Writing RegFrfLsb will trigger the frequency change.
0
 Frf is validated when FSTx or FSRx is requested
1
 Frf is validated triggered when RegFrfLsb is written
6-0 reserved rw 0x2E reserved
RegTcxo
(0x58)
7-5 reserved rw 0x00 reserved. Retain default value
4 TcxoInputOn rw 0x00
Controls the crystal oscillator
0  Crystal Oscillator with external Crystal
1
 External clipped sine TCXO AC-connected to XTA pin
3-0 reserved rw 0x09 Reserved. Retain default value.
RegPaDac
(0x5A)
7-3 reserved rw 0x10 reserved. Retain default value
2-0 PaDac rw 0x04
Enables the +20 dBm option on PA_BOOST pin
0x04  Default value
0x07
 +20 dBm on PA_BOOST when OutputPower = 1111
Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description