Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History

www.semtech.comPage 39
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
The software packet filtering process follows the steps below:
Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable, this
variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the SX1272 gives in real time the address
of the last byte written in the data buffer + 1 (or the address at which the next byte will be written by the receive LoRa
TM
modem). So by doing this, we make sure that the variable start_address always contains the start address of the next
packet.
Upon reception of the interrupt ValidHeader, start polling the RegFifoRxByteAddr[7:0] register until it begins to
increment. The speed at which this register will increment depends on the spreading factor, the error correction code
and the modulation bandwidth. (Note that this interrupt is still generated in implicit mode).
As soon as RegFifoRxByteAddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the FIFO data buffer.
These can be read and tested to see if the packet is destined for the radio and either remaining in Rx mode to receive
the packet or returning to sleep mode if not.
Receiver Timeout Operation
In either single or continuous LoRa
TM
reception modes, a receiver timeout functionality is available that permits the receiver
to listen for a predetermined period of time before generating an interrupt signal to indicate that no valid packets have been
received. The timer is absolute and commences as soon as the radio is placed in either single or continuous receive mode.
The interrupt itself,
RxTimeout, can be found in the interrupt register RegIrqFlags. In Rx Single mode, the device will return
to Standby mode as soon as the interrupt occurs and the interrupt needs to be cleared before returning to Rx Single mode.
In Rx Continuous mode, the interrupt will simply be raised but the device will stay in Rx Continuous mode. It is therefore the
responsibility on the companion microcontroller to clear the interrupt while still in Rx Continuous mode. The programmed
timeout value is expressed as a multiple of the symbol period and is given by:
TimeOut LoraRxTimeout Ts⋅=