Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History
www.semtech.comPage 42
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
To illustrate this process and the respective consumption in each mode, the CAD process follows the sequence of events
outlined below:
Figure 14. Consumption Profile of the LoRa CAD Process
The receiver is then in full receiver mode for just over half of the activity detection, followed by a reduced consumption
processing phase where the consumption varies with the LoRa bandwidth as shown in the table below.
Table 16 LoRa CAD Consumption Figures
4.1.6.1. Digital IO Pin Mapping
Six of SX1272/73’s general purpose IO pins are available used in LoRa
TM
mode. Their mapping is shown below and
depends upon the configuration of registers RegDioMapping1 and RegDioMapping2.
Table 17 DIO Mapping LoRa
TM
Mode
Bandwidth
(kHz)
Full Rx, IDDR_L
(mA)
Processing, IDDC_L
(mA)
125 10.8 5.6
250 11.6 6.5
500 13 8
Operating
Mode
DIOx
Mapping
DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
ALL
00
ModeReady CadDetected CadDone FhssChangeChannel RxTimeout RxDone
01
ClkOut PllLock ValidHeader FhssChangeChannel FhssChangeChannel TxDone
10
ClkOut PllLock PayloadCrcError FhssChangeChannel CadDetected CadDone
11
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