Datasheet

Table Of Contents

www.semtech.comPage 62

SX1272/73

WIRELESS, SENSING & TIMING DATASHEET

Rev. 2 - July 2014

4.2.11. FIFO

Overview and Shift Register (SR)

In packet mode of operation both data to be transmitted and that has been received are stored in a configurable FIFO (First

In First Out). It is accessed via the SPI interface and provides several interrupts for transfer management.

The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A

shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs

them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data

from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.

Figure 27. FIFO and Shift Register (SR)

Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (immediately from all

modes except from Tx)

The FIFO size is fixed to 64 bytes.

Interrupt Sources and Flags

 FifoEmpty: FifoEmpty interrupt source is high when byte 0, i.e. whole FIFO, is empty. Otherwise it is low. Note that when

retrieving data from the FIFO, FifoEmpty is updated on NSS falling edge, i.e. when FifoEmpty is updated to low state

the currently started read operation must be completed. In other words, FifoEmpty state must be checked after each

read operation for a decision on the next one (FifoEmpty = 0: more byte(s) to read; FifoEmpty = 1: no more byte to

read).

 FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.

 FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (in

Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will

also be cleared.

 PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.

 FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.

Data Tx/Rx

SR (8bits)

byte0

byte1

FIFO

MSB

LSB