Datasheet

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SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
4.2.12. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1272/73 and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
Table 28 DIO Mapping, Continuous Mode
Table 29 DIO Mapping, Packet Mode
DIOx Mapping Sleep Standby FSRx/Tx Rx Tx
00 SyncAddress TxReady
01 Rssi / PreambleDetect -
10 RxReady TxReady
11
00
01 Rssi / PreambleDetect -
10
11
00
01
10
11
00 Timeout -
01 Rssi / PreambleDetect -
10
11 -
00
01
10 TimeOut -
11 -
00 ClkOut if RC
01
10 Rssi / PreambleDetect -
11 -
PllLock
ModeReady ModeReady
DIO0
DIO1
DIO3
DIO2
-
-
-
DIO5
DIO4
-
-
-
-
-
-
-
-
-
-
-
-
ModeReady ModeReady
Dclk
Data
Data
Data
ClkOut ClkOut
TempChange / LowBat TempChange / LowBat
TempChange / LowBat
PllLock
Data
-
-
-
-
-
DIOx Mapping Sleep Standby FSRx/Tx Rx Tx
00
PayloadReady PacketSent
01 CrcOk -
10
11 -
00 FifoLevel
01 FifoEmpty
10 FifoFull
11
00 FifoFull
01 RxReady -
10 TimeOut FifoFull
11 SyncAddress FifoFull
00 FifoEmpty
01 TxReady
10 FifoEmpty
11 FifoEmpt
y
00 -
01
10 TimeOut -
11 Rssi / PreambleDetect -
00 ClkOut if RC
01
10
11 -
FifoEmpty
ModeReady
FifoEmpty
FifoEmpty
FifoEmpty
DIO5
- PllLock
-Data
ClkOut ClkOut
ModeReady
DIO4
- PllLock
-
-
TempChange / LowBat TempChange / LowBat
DIO3
-
FifoEmpty
DIO2
-
FifoFull
FifoFull
FifoFull FifoFull
FifoEmpty
DIO1
-
FifoLevel
FifoEmpty FifoEmpty
FifoLevel
FifoFull FifoFull
DIO0
-
-
-
TempChange / LowBatTempChange / LowBat