Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History
www.semtech.comPage 66
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
4.2.13. Continuous Mode
4.2.13.1. General Description
As illustrated in Figure 30 in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on
the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive.
Figure 30. Continuous Mode Conceptual View
4.2.13.2. Tx Processing
In Tx mode a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the
data is illustrated in
Figure 31. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state
anytime outside the grayed out setup/hold zone.
Figure 31. Tx Processing in Continuous Mode
Note the use of DCLK is required when the modulation shaping is enabled (see section 4.2.13.2).
CONTROL
SPI
SYNC
RECOG.
DIO1/DCLK
MISO
MOSI
SCK
NSS
Rx
Tx/Rx
Data
DIO2/DATA
DIO0
DIO3
DIO4
DIO5
DCLK
T_DATAT_DATA
DATA
(NRZ)