Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History

www.semtech.comPage 79
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
5.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note To minimize the current consumption of the SX1272/73, please ensure that the CLKOUT signal is disabled when
not required.
5.3.3. PLL
The local oscillator of the SX1272/73 is derived from a fractional-N PLL that is referenced to the crystal oscillator circuit.
Two PLLs are available for transmit mode operation - either low phase noise or low current consumption to maximize either
transmit power consumption or transmit spectral purity respectively. Both PLLs feature a programmable bandwidth setting
where one of four discrete preset bandwidths may be accessed. For reference the relative performance of both low
consumption and low phase noise PLLs, for each programmable bandwidth setting, is shown in the following figure.