Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History
www.semtech.comPage 90
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
6. Description of the Registers
The register mapping depends upon whether FSK/OOK or LoRa
TM
mode has been selected. The following table
summarises the location and function of each register and gives an overview of the changes in register mapping between
both modes of operation.
6.1. Register Table Summary
Table 39 Registers Summary
Address
Register Name
Reset
(POR)
Default
(FSK)
Description
FSK/OOK Mode
LoRa
TM
Mode
FSK Mode
LoRa
TM
Mode
0x00 RegFifo 0x00 FIFO read/write access
0x01 RegOpMode 0x01
Operating mode & LoRa
TM
/ FSK selection
0x02 RegBitrateMsb
Unused
0x1A Bit Rate setting, Most Significant Bits
0x03 RegBitrateLsb 0x0B Bit Rate setting, Least Significant Bits
0x04 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits
0x05 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits
0x06 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits
0x07 RegFrfMid 0xC0 RF Carrier Frequency, Intermediate Bits
0x08 RegFrfLsb 0x00 RF Carrier Frequency, Least Significant Bits
0x09 RegPaConfig 0x0F PA selection and Output Power control
0x0A RegPaRamp 0x19 Control of PA ramp time, low phase noise PLL
0x0B RegOcp 0x2B Over Current Protection control
0x0C RegLna 0x20 LNA settings
0x0D RegRxConfig RegFifoAddrPtr 0x08 0x1E AFC, AGC, ctrl FIFO SPI pointer
0x0E RegRssiConfig
RegFifoTxBa-
seAddr
0x02 RSSI Start Tx data
0x0F RegRssiCollision
RegFifoRxBa-
seAddr
0x0A RSSI Collision detector Start Rx data
0x10 RegRssiThresh
FifoRxCurren-
tAddr
0xFF RSSI Threshold control
Start address of last
packet received
0x11 RegRssiValue RegIrqFlagsMask n/a n/a RSSI value in dBm Optional IRQ flag mask
0x12 RegRxBw RegIrqFlags 0x15 Channel Filter BW Control IRQ flags
0x13 RegAfcBw RegRxNbBytes 0x0B AFC Channel Filter BW Number of received bytes
0x14 RegOokPeak
RegRxHeaderCnt
ValueMsb
0x28 OOK demodulator
Number of valid headers
received
0x15 RegOokFix
RegRxHeaderCnt
ValueLsb
0x0C Threshold of the OOK demod
0x16 RegOokAvg
RegRxPacketCnt
ValueMsb
0x12 Average of the OOK demod
Number of valid packets
received
0x17 Reserved17
RegRxPacketCnt
ValueLsb
0x47 -
0x18 Reserved18 RegModemStat 0x32 -
Live LoRaTM modem
status
0x19 Reserved19 RegPktSnrValue 0x3E -
Espimation of last packet
SNR
0x1A RegAfcFei RegPktRssiValue 0x00 n/a AFC and FEI control RSSI of last packet