Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History
www.semtech.comPage 91
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
0x1B RegAfcMsb RegRssiValue 0x00 n/a
Frequency correction value of
the AFC
Current RSSI
0x1C RegAfcLsb RegHopChannel 0x00 n/a FHSS start channel
0x1D RegFeiMsb
RegModemConfig
1
0x00
n/a
Value of the calculated
frequency error
Modem PHY config 1
0x1E RegFeiLsb
RegModemConfig
2
0x00
n/a
Modem PHY config 2
0x1F RegPreambleDe-
tect
RegSymbTimeout
Lsb
0x40
0xAA
Settings of the Preamble
Detector
Receiver timeout value
0x20 RegRxTimeout1 RegPreambleMsb 0x00 Timeout Rx request and RSSI
Size of preamble
0x21 RegRxTimeout2 RegPreambleLsb 0x00 Timeout RSSI and Pay-
loadReady
0x22 RegRxTimeout3 RegPay-
loadLength
0x00 Timeout RSSI and SyncAd-
dress
LoRaTM payload length
0x23 RegRxDelay
RegMaxPayloadL
ength
0x00
Delay between Rx cycles
LoRaTM maximum pay-
load length
0x24 RegOsc RegHopPeriod 0x05
0x07
RC Oscillators Settings, CLK-
OUT frequency
FHSS Hop period
0x25 RegPreambleMsb
RegFifoRxByteAd
dr
0x00
Preamble length, MSB
Address of last byte
written in FIFO
0x26 RegPreambleLsb
RESERVED
0x03
Preamble length, LSB
LoRa
TM
rx data pointer
0x27 RegSyncConfig 0x93
Sync Word Recognition control RESERVED
0x28 RegSyncValue1 RegFeiMsb 0x55
0x01
Sync Word bytes, 1 through 8
Estimated frequency
error
0x29 RegSyncValue2 RegFeiMib 0x55
0x01
0x2A RegSyncValue3 RegFeiLsb 0x55
0x01
0x2B-
0x2F
RegSyncValue4
RESERVED
0x55
0x01
RESERVED
0x2C RegSyncValue5 RegRssiWide-
band
0x55
0x01
Wideband RSSI meas-
urement
0x2D-
2F
RegSyncValue6-8
RESERVED
0x55
0x01
RESERVED
0x30 RegPacketConfig1 0x90 Packet mode settings
0x31 RegPacketConfig2 RegDetectOpti-
mize
0x40
Packet mode settings
LoRa detection Optimize
for SF6
0x32 RegPayloadLength RESERVED 0x40 Payload length setting RESERVED
0x33 RegNodeAdrs RegInvertIQ 0x00
Node address
Invert LoRa I and Q sig-
nals
0x34 RegBroadcastAdrs
RESERVED
0x00 Broadcast address
RESERVED
0x35 RegFifoThresh 0x0F
0x8F
Fifo threshold, Tx start condi-
tion
0x36 RegSeqConfig1 0x00 Top level Sequencer settings
0x37 RegSeqConfig2 RegDetection-
Threshold
0x00
Top level Sequencer settings
Change the LoRa Detec-
tion threshold for SF6
Address
Register Name
Reset
(POR)
Default
(FSK)
Description
FSK/OOK Mode
LoRa
TM
Mode
FSK Mode
LoRa
TM
Mode