Datasheet

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SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
Notes - Reset values are automatically refreshed in the chip at Power On Reset
- Default values are the Semtech recommended register values, optimizing the device operation
- Registers for which the Default value differs from the Reset value are denoted by an * in the tables of section 6.2
0x38 RegTimerResol
RESERVED
0x00 Timer 1 and 2 resolution control
RESERVED
0x39 RegTimer1Coef 0xF5 Timer 1 setting
0x3A RegTimer2Coef 0x20 Timer 2 setting
0x3B RegImageCal 0x82
0x02
Image calibration engine con-
trol
0x3C RegTemp - Temperature Sensor value
0x3D RegLowBat 0x02 Low Battery Indicator Settings
0x3E RegIrqFlags1 0x80
n/a
Status register: PLL Lock state,
Timeout, RSSI
0x3F RegIrqFlags2 0x40
n/a
Status register: FIFO handling
flags, Low Battery
0x40 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3
0x41 RegDioMapping2 0x00 Mapping of pins DIO4 and DIO5, ClkOut frequency
0x42 RegVersion 0x22 Semtech ID relating the silicon revision
0x43 RegAgcRef 0x13
Adjustment of the AGC thresholds
0x44 RegAgcThresh1 0x0E
0x45 RegAgcThresh2 0x5B
0x46 RegAgcThresh3 0xDB
0x4B RegPllHop 0x2E Control the fast frequency hopping mode
0x58 RegTcxo 0x09 TCXO or XTAL input setting
0x5A RegPaDac 0x84 Higher power settings of the PA
0x5C RegPll 0xD0 Control of the PLL bandwidth
0x5E RegPllLowPn 0xD0 Control of the Low Phase Noise PLL bandwidth
0x6C RegFormerTemp - Stored temperature during the former IQ Calibration
0x70 RegBitRateFrac 0x00 Fractional part in the Bit Rate division ratio
Address
Register Name
Reset
(POR)
Default
(FSK)
Description
FSK/OOK Mode
LoRa
TM
Mode
FSK Mode
LoRa
TM
Mode