Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History

www.semtech.comPage 97
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
RegOokFix
(0x15)
7-0 OokFixedThreshold rw 0x0C
Fixed threshold for the Data Slicer in OOK mode
Floor threshold for the Data Slicer in OOK when Peak mode is
used
RegOokAvg
(0x16)
7-5 OokPeakThreshDec rw 0x00
Period of decrement of the RSSI threshold in the OOK
demodulator:
000 once per chip 001 once every 2 chips
010 once every 4 chips 011 once every 8 chips
100 twice in each chip 101 4 times in each chip
110 8 times in each chip 111 16 times in each chip
4 reserved rw 0x01 reserved
3-2 OokAverageOffset rw 0x00
Static offset added to the threshold in average mode in order to
reduce glitching activity (OOK only):
00
0.0 dB 10 4.0 dB
01
2.0 dB 11 6.0 dB
1-0 OokAverageThreshFilt rw 0x02
Filter coefficients in average mode of the OOK demodulator:
00 f
C
≈ chip rate / 32.π 01 f
C
≈ chip rate / 8.π
10 f
C
≈ chip rate / 4.π 11 f
C
≈ chip rate / 2.π
RegRes17
to
RegRes19
7-0 reserved rw
0x47
0x32
0x3E
reserved. Keep the Reset values.
RegAfcFei
(0x1A)
7-5 unused r - unused
4 AgcStart wt 0x00 Triggers an AGC sequence when set to 1.
3 reserved rw 0x00 reserved
2 unused - - unused
1 AfcClear wc 0x00 Clear AFC register set in Rx mode. Always reads 0.
0 AfcAutoClearOn rw 0x00
Only valid if AfcAutoOn is set
0
AFC register is not cleared at the beginning of the automatic
AFC phase
1
AFC register is cleared at the beginning of the automatic
AFC phase
RegAfcMsb
(0x1B)
7-0 AfcValue(15:8) rw 0x00
MSB of the AfcValue, 2’s complement format. Can be used to
overwrite the current AFC value
RegAfcLsb
(0x1C)
7-0 AfcValue(7:0) rw 0x00
LSB of the AfcValue, 2’s complement format. Can be used to
overwrite the current AFC value
RegFeiMsb
(0x1D)
7-0 FeiValue(15:8) rw -
MSB of the measured frequency offset, 2’s complement. Must be
read before RegFeiLsb.
RegFeiLsb
(0x1E)
7-0 FeiValue(7:0) rw -
LSB of the measured frequency offset, 2’s complement
Frequency error = FeiValue x Fstep
Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description