Datasheet
Table Of Contents
- 1. General Description
- 2. Electrical Characteristics
- 3. SX1272/73 Features
- 4. SX1272/73 Digital Electronics
- 4.1. The LoRaTM Modem
- 4.2. FSK/OOK Modem
- 4.2.1. Bit Rate Setting
- 4.2.2. FSK/OOK Transmission
- 4.2.3. FSK/OOK Reception
- 4.2.4. Operating Modes in FSK/OOK Mode
- 4.2.5. General Overview
- 4.2.6. Startup Times
- 4.2.7. Receiver Startup Options
- 4.2.8. Receiver Restart Methods
- 4.2.9. Top Level Sequencer
- 4.2.10. Data Processing in FSK/OOK Mode
- 4.2.11. FIFO
- 4.2.12. Digital IO Pins Mapping
- 4.2.13. Continuous Mode
- 4.2.14. Packet Mode
- 4.2.15. io-homecontrol® Compatibility Mode
- 4.3. SPI Interface
- 5. SX1272/73 Analog & RF Frontend Electronics
- 6. Description of the Registers
- 7. Application Information
- 8. Packaging Information
- 9. Revision History
www.semtech.comPage 98
SX1272/73
WIRELESS, SENSING & TIMING DATASHEET
Rev. 2 - July 2014
©2014 Semtech Corporation
RegPreambleDetect
(0x1F)
7 PreambleDetectorOn rw
0x01
*
Enables Preamble detector when set to 1. The AGC settings
supersede this bit during the startup / AGC phase.
0
Turned off
1
Turned on
6-5 PreambleDetectorSize rw
0x01
*
Number of Preamble bytes to detect to trigger an interrupt
00 1 byte 10 3 bytes
01
2 bytes 11 Reserved
4-0 PreambleDetectorTol rw
0x0A
*
Number or chip errors tolerated over PreambleDetectorSize.
4 chips per bit.
RegRxTimeout1
(0x20)
7-0 TimeoutRxRssi rw 0x00
Timeout interrupt is generated TimeoutRxRssi*16*T
bit
after
switching to Rx mode if
Rssi interrupt doesn’t occur (i.e.
RssiValue > RssiThreshold)
0x00: TimeoutRxRssi is disabled
RegRxTimeout2
(0x21)
7-0 TimeoutRxPreamble rw 0x00
Timeout interrupt is generated TimeoutRxPreamble*16*T
bit
after
switching to Rx mode if
Preamble interrupt doesn’t occur
0x00: TimeoutRxPreamble is disabled
RegRxTimeout3
(0x22)
7-0 TimeoutSignalSync rw 0x00
Timeout interrupt is generated TimeoutSignalSync*16*T
bit
after
the Rx mode is programmed, if
SyncAddress doesn’t occur
0x00: TimeoutSignalSync is disabled
RegRxDelay
(0x23)
7-0 InterPacketRxDelay rw 0x00
Additional delay before an automatic receiver restart is launched:
Delay = InterPacketRxDelay*4*Tbit
RC Oscillator registers
RegOsc
(0x24)
7-4 unused r - unused
3 RcCalStart wt 0x00
Triggers the calibration of the RC oscillator when set. Always
reads 0. RC calibration must be triggered in Standby mode.
2-0 ClkOut rw
0x07
*
Selects CLKOUT frequency:
000 FXOSC
001 FXOSC / 2
010 FXOSC / 4
011 FXOSC / 8
100 FXOSC / 16
101 FXOSC / 32
110 RC (automatically enabled)
111 OFF
Packet Handling registers
RegPreambleMsb
(0x25)
7-0 PreambleSize(15:8) rw 0x00
Size of the preamble to be sent (from
TxStartCondition fulfilled).
(MSB byte)
RegPreambleLsb
(0x26)
7-0 PreambleSize(7:0) rw 0x03
Size of the preamble to be sent (from
TxStartCondition fulfilled).
(LSB byte)
Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description