Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsCD4052BPWR Interface IC - multiplexer, demultiplexer TSSOP 16

INH

C B A

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Ch 0

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

C B A

COM

ax OR ay

bx OR by

cx OR cy

INH

X COM

Y COM

B A

0 0

0 1

1 0

1 1

Ch X0

Ch Y0

Ch X1

Ch Y1

Ch X2

Ch Y2

Ch X3

Ch Y3

CD4051B

CD4052B

CD4053B

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CD4051B

CD4052B

CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

With Logic-Level Conversion

1 Features

• Wide Range of Digital and Analog Signal Levels

– Digital: 3 V to 20 V

– Analog: ≤20 V

P-P

• Low ON Resistance,125 Ω (Typical) Over 15 V

P-P

Signal Input Range for V

– V

= 18 V

• High OFF Resistance, Channel Leakage of ±100

pA (Typical) at V

– V

= 18 V

• Logic-Level Conversion for Digital Addressing

Signals of 3 V to 20 V (V

– V

= 3 V to 20 V)

to Switch Analog Signals to 20 V

P-P

– V

20 V) Matched Switch Characteristics, r

= 5 Ω

(Typical) for V

– V

= 15 V Very Low Quiescent

Power Dissipation Under All Digital-Control Input

and Supply Conditions, 0.2 µW (Typical) at V

–

= V

– V

= 10 V

• Binary Address Decoding on Chip

• 5 V, 10 V, and 15 V Parametric Ratings

• 100% Tested for Quiescent Current at 20 V

• Maximum Input Current of 1 µA at 18 V Over Full

Package Temperature Range, 100 nA at 18 V and

25°C

• Break-Before-Make Switching Eliminates Channel

Overlap

2 Applications

• Analog and Digital Multiplexing and

Demultiplexing

• A/D and D/A Conversion

• Signal Gating

• Factory Automation

• Televisions

• Appliances

• Consumer Audio

• Programmable Logic Circuits

• Sensors

3 Description

The CD405xB analog multiplexers and demuliplexers

are digitally-controlled analog switches having low

ON impedance and very low OFF leakage current.

These multiplexer circuits dissipate extremely low

quiescent power over the full V

– V

and V

–

supply-voltage ranges, independent of the logic

state of the control signals.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

CD405xB

CDIP (16) 19.50 mm × 6.92 mm

PDIP (16) 19.30 mm × 6.35 mm

SOIC (16) 9.90 mm × 3.91 mm

SOP (16) 10.30 mm × 5.30 mm

TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Diagrams of CD405xB

Summary of content (37 pages)

PAGE 1
Product Folder Order Now Support & Community Tools & Software Technical Documents CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer With Logic-Level Conversion 1 Features 3 Description • The CD405xB analog multiplexers and demuliplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications........................
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CD4051B, CD4052B, CD4053B www.ti.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com Pin Functions CD4052B PIN I/O DESCRIPTION NO.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply Voltage V+ to V-, Voltages Referenced to VSS Terminal DC Input Voltage DC Input Current MIN MAX UNIT –0.5 20 V –0.5 VDD + 0.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com 6.5 Electrical Characteristics over operating free-air temperature range, VSUPPLY = ±5 V, and RL = 100 Ω, (unless otherwise noted) (1) TEST CONDITIONS MIN TYP MAX UNIT PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) TEMP SIGNAL INPUTS (VIS) AND OUTPUTS (VOS) –55°C 5 –40°C 5 25°C 5 0.04 150 125°C 150 –55°C 10 –40°C 10 Quiescent Device Current, IDD Max 5 85°C 25°C 10 0.
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CD4051B, CD4052B, CD4053B www.ti.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com 6.6 AC Performance Characteristics PARAMETER TEST CONDITIONS VIS (V) VDD (V) RL (kΩ) 5 (1) 10 1 Cutoff (–3dB) Frequency Channel ON (Sine Wave Input) VOS at Common OUT/IN CD4053 30 CD4052 25 CD4051 20 VOS at Any Channel VOS = – 3 dB VIS 2 (1) 5 3 (1) 10 5 (1) 15 UNIT MHz VEE = VSS , 20 Log Total Harmonic Distortion, THD TYP 60 0.3% 10 0.2% 0.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 6.7 Typical Characteristics 300 VDD - VEE = 5V rON , CHANNEL ON RESISTANCE (Ω) rON , CHANNEL ON RESISTANCE (Ω) 600 500 400 TA = 125oC 300 TA = 25oC 200 TA = -55oC 100 250 150 TA = 25oC 100 TA = -55oC 50 0 -10 0 -4 -3 -2 -1 0 1 2 3 4 5 -7.5 rON , CHANNEL ON RESISTANCE (Ω) TA = 25oC VDD - VEE = 5V 500 400 300 200 10V 15V 100 0 -10 -7.5 -5 -2.5 0 2.5 5 7.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF 104 f VDD = 15V 103 VDD = 10V 102 VDD = 5V CL = 15pF 10 1 10 TEST CIRCUIT VDD CD4029 VDD B/D A B 100Ω 10 9 1 3 CL 13 5 12 2 4 CD4052 14 15 6 11 7 8 Ι 102 103 104 SWITCHING FREQUENCY (kHz) 105 Figure 7.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 7 Parameter Measurement Information VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V 5V 7.5V 16 5V 16 16 16 VSS = 0V VSS = 0V VSS = 0V VEE = 0V 7 8 7 8 VEE = -7.5V VEE = -10V 7 8 VEE = -5V 7 8 VSS = 0V (D) (C) (B) (A) Figure 9. Typical Bias Voltages NOTE The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS and 1 = VDD. The analog signal (through the TG) may swing from VEE to VDD.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com VDD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IDD VDD IDD CD4051 VDD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CD4053 CD4052 Copyright © 2017, Texas Instruments Incorporated Figure 13. On Channel Leakage Current - Any Channel On Figure 14.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 VDD VDD VDD µA VIH 1K VIH 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1K VIL 1 2 3 4 5 6 7 8 VIH VIL 15 14 13 12 11 10 9 1K 1K µA VIH 1K VIL VIH VIL 16 15 14 13 12 11 10 9 1K µA VIH VIL CD4053B CD4052B CD4051B 1 2 3 4 5 6 7 8 VIL MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 6) MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL by) MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 5VP-P www.ti.com OFF CHANNEL 5VP-P CHANNEL ON RF VM COMMON 1K CHANNEL OFF RF VM RL VDD RL 6 7 8 RL RL Figure 21. Feedthrough (All Types) 5VP-P CHANNEL ON RF VM CHANNEL OFF Figure 22. Crosstalk Between Any Two Channels (All Types) CHANNEL IN Y ON OR OFF CHANNEL IN X ON OR OFF RL RF VM RL Figure 23. Crosstalk Between Duals or Triplets (CD4052B, CD4053B) DIFFERENTIAL SIGNALS CD4052 CD4052 LINK DIFF.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 8 Detailed Description 8.1 Overview The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved by digital signal amplitudes of 4.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com Functional Block Diagrams (continued) X CHANNELS IN/OUT 3 2 1 0 11 15 14 12 TG 16 VDD A TG TG COMMON X OUT/IN TG 13 10 B 9 INH 6 BINARY TO 1 OF 4 DECODER WITH INHIBIT LOGIC LEVEL CONVERSION 3 TG TG COMMON Y OUT/IN TG TG 8 VSS 7 VEE 1 5 2 4 0 1 2 3 Y CHANNELS IN/OUT All inputs are protected by standard CMOS protection network. Figure 27.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 8.3 Feature Description The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels. Digital signals range from 3 V to 20 V, and analog signals are accepted at levels ≤ 20 V. They have low ON resistance, typically 125 Ω over 15 VP-P signal input range for VDD – VEE = 18 V. This allows for very little signal loss through the switch.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 Typical Application (continued) 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – For switch time specifications, see propagation delay times in Electrical Characteristics. – Inputs should not be pushed more than 0.5 V above VDD or below VEE. – For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics. 2.
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CD4051B, CD4052B, CD4053B SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 www.ti.com 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width.
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CD4051B, CD4052B, CD4053B www.ti.com SCHS047I – AUGUST 1998 – REVISED SEPTEMBER 2017 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation • Implications of Slow or Floating CMOS Inputs, SCBA004 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Jul-2017 Status (1) CD4053BPWRG4 ACTIVE Package Type Package Pins Package Drawing Qty TSSOP PW 16 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 125 CM053B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD4053BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4053BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4053BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4052BM96 SOIC D 16 2500 333.2 345.9 28.6 CD4052BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4052BM96G4 SOIC D 16 2500 333.2 345.9 28.6 CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4052BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4052BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 CD4052BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.