Datasheet

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Typical Connection

Product Summary

OFFSET

600V max.

+/- 120 mA / 250 mA

OUT

10 - 20V

on/off

(typ.) 180 ns

Delay matching 50 ns

HIGH AND LOW SIDE DRIVER

Features

•

Floating channel designed for bootstrap operation

Fully operational to +600V

Tolerant to negative transient voltage

dV/dt immune

•

Gate drive supply range from 10 to 20V (IR2106(4))

•

Undervoltage lockout for both channels

•

3.3V, 5V and 15V input logic compatible

•

Matched propagation delay for both channels

•

Logic and power ground +/- 5V offset.

•

Lower di/dt gate driver for better noise immunity

•

Outputs in phase with inputs (IR2106)

Description

The IR2106(4)(S) are high voltage, high speed power

MOSFET and IGBT drivers with independent high and

low side referenced output channels. Proprietary HVIC

and latch immune CMOS technologies enable rug-

gedized monolithic construction. The logic input is

compatible with standard CMOS or LSTTL output,

down to 3.3V logic. The output drivers feature a high

pulse current buffer stage designed for minimum driver

cross-conduction. The floating channel can be used

to drive an N-channel power MOSFET or IGBT in the

high side configuration which operates up to 600 volts.

Packages

14-Lead PDIP

14-Lead SOIC

IR2106(4)

(

)

8-Lead PDIP

8-Lead SOIC

www.irf.com 1

IR2106

LOCOM

HIN

LIN

up to 600V

LOAD

LIN

HIN

IR21064

up to 600V

LOAD

COM

HIN

LIN

HIN

Data Sheet No. PD60162-T

(Refer to Lead Assignments for correct pin

configuration). This/These diagram(s) show

electrical connections only. Please refer to our

Application Notes and DesignTips for proper

circuit board layout.

Summary of content (18 pages)

PAGE 1
Data Sheet No. PD60162-T IR2106(4)(S) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • Product Summary Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V (IR2106(4)) Undervoltage lockout for both channels 3.3V, 5V and 15V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5V offset.
PAGE 2
IR2106(4) (S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating absolute voltage VS Max. -0.3 625 Units High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.
PAGE 3
IR2106(4) (S) Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential. Symbol Definition VB High side floating supply absolute voltage IR2106(4) VS High side floating supply offset voltage Min. Max.
PAGE 4
IR2106(4) (S) Static Electrical Characteristics VBIAS (V CC , VBS ) = 15V, V SS = COM and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VSS/COM and are applicable to the respective input leads. The VO, I O and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition VIH Logic “1” input voltage (IR2106(4)) VIL Min. Typ. Max. Units Test Conditions 2.
PAGE 5
IR2106(4) (S) Functional Block Diagrams VB UV DETECT IR2106 HO R HIN VSS/COM LEVEL SHIFT HV LEVEL SHIFTER R PULSE FILTER Q S VS PULSE GENERATOR VCC UV DETECT LIN VSS/COM LEVEL SHIFT LO DELAY COM VB UV DETECT IR21064 HO R HIN VSS/COM LEVEL SHIFT HV LEVEL SHIFTER R PULSE FILTER Q S VS PULSE GENERATOR VCC UV DETECT LIN VSS/COM LEVEL SHIFT DELAY LO COM VSS www.irf.
PAGE 6
IR2106(4) (S) Lead Definitions Symbol Description HIN Logic input for high side gate driver output (HO), in phase LIN Logic input for low side gate driver output (LO), in phase VSS Logic Ground (IR21064 only) VB High side floating supply HO High side gate drive output VS High side floating supply return VCC Low side and logic fixed supply LO Low side gate drive output COM Low side return Lead Assignments VB 8 1 HIN HO 7 2 3 LIN VS 6 4 COM LO 5 1 VCC 2 1 4 8 HIN HO 7
PAGE 7
IR2106(4) (S) HIN LIN HO LO Figure 1. Input/Output Timing Diagram 50% 50% HIN LIN ton toff tr 90% HO LO tf 90% 10% 10% Figure 2. Switching Time Waveform Definitions HIN LIN 50% 50% LO HO 10% MT MT 90% LO HO Figure 3. Delay Matching Waveform Definitions www.irf.
PAGE 8
IR2106(4) (S) 500 Turn-on Propagation Delay (ns) Turn-on Propagation Delay (ns) 500 400 300 M ax 200 Typ. 100 400 M ax. 300 Typ. 200 100 0 0 -50 -25 0 25 50 75 100 125 10 12 Temperature ( oC) Figure 4A. Turn-on Propagation Delay vs. Temperature 18 20 500 Turn-off Propagation Delay (ns) Turn-off Propagation Delay (ns) 16 Figure 4B. Turn-on Propagation Delay vs. Supply Voltage 500 400 300 M ax. 200 Typ. 100 0 400 M ax. 300 Typ.
PAGE 9
IR2106(4) (S) 500 400 Turn-on Rise Time (ns) Turn-on Rise Time (ns) 500 300 200 M ax. Typ. 100 400 300 M ax. Typ. 200 100 0 0 -50 -25 0 25 50 75 100 10 125 12 Temperature ( oC) 16 18 20 V BIAS Supply Voltage (V) Figure 6A. Turn-on Rise Time vs. Temperature Figure 6B. Turn-on Rise Time vs. Supply Voltage 200 Turn-off Fall Time (ns) 200 Turn-off Fall Time (ns) 14 150 100 M ax. 50 Typ. 0 150 100 M ax. Typ.
PAGE 10
8 8 7 7 6 6 Input Voltage (V) Input Voltage (V) IR2106(4) (S) 5 4 M ax. 3 2 1 5 4 M ax. 3 2 1 0 0 -50 -25 0 25 50 75 100 125 10 12 Temperature (oC) 14 16 18 20 V CC Supply Voltage (V) Figure 8A. Logic “1” Input Voltage vs. Temperature Figure 8B. Logic “1” Input Voltage vs. Supply Voltage 4.0 4.0 3.2 Input Voltage (V) Input Voltage (V) 3.2 2.4 1.6 M in. 0.8 1.6 M in. 0.8 0.0 0.0 -50 -25 0 25 50 75 100 Temperature ( oC) Figure 9A. Logic “0” Input Voltage vs.
PAGE 11
IR2106(4) (S) 4 High Level Output Voltage (V) High Level Output Voltage (V) 4 3 2 M ax. 1 Typ. 0 3 M ax. 2 Typ. 1 0 -50 -25 0 25 50 75 100 125 10 12 Temperature ( oC) Figure 10A. High Level Output Voltage vs. Temperature 16 18 20 Figure 10B. High Level Output Voltage vs. Supply Voltage 1.5 1.5 Low Level Output Voltage (V) Low Level Output Voltage (V) 14 V BIAS Supply Voltage (V) 1.2 0.9 0.6 M ax. 0.3 Typ. 0 1.2 0.9 M ax. 0.6 Typ. 0.
PAGE 12
500 Offset Supply Leakage Current ( A) Offset Supply Leakage Current ( A) IR2106(4) (S) 400 300 200 100 M ax. 0 -50 -25 0 25 50 75 100 500 400 300 200 100 M ax. 0 125 0 100 o Temperature ( C) 400 500 600 Figure 12B. Offset Supply Leakage Current vs. Supply Voltage 400 V BS Supply Current ( A) 400 V BS Supply Current ( A) 300 V B Boost Voltage (V) Figure 12A. Offset Supply Leakage Current vs. Temperature 300 200 M ax. 100 Typ. 300 200 M ax. 100 Typ. M in. M in.
PAGE 13
IR2106(4) (S) 400 V CC Supply Current ( A) V c c S u p p ly C u rre n t ( A ) 400 300 200 M ax. Typ. 100 M in. 300 M ax. 200 Typ. M in. 100 0 0 -50 -25 0 25 50 75 100 125 10 12 T e m p e ra tu re (oC ) 18 20 Figure 14B. Quiescent VCC Supply Current vs. VCC Supply Voltage 60 60 Logic "1" Input Current ( A) Logic "1" Input Current ( A) 16 V CC Supply Voltage (V) Figure 14A. Quiescent VCC Supply Current vs. Temperature 50 40 30 20 10 14 M ax. 50 40 30 M ax.
PAGE 14
IR2106(4) (S) 5 Logic "0" Input Current ( A) Logic "0" Input Current ( A) 5 4 3 M ax. 2 1 4 3 M ax. 2 1 0 0 -50 -25 0 25 50 75 100 125 10 12 Fi 16B L Figure 16A. Logic “0” Input Current vs. Temperature 12 18 20 i "0" I C Figure 16B. Logic “0” Input Currentt vs. Supply Voltage 11 V CC UVLO Threshold (-) (V) V CC UVLO Threshold (+) (V) 16 V CC Supply Voltage (V) Temperature (oC) 11 10 M ax. Typ. 9 M in. 8 7 10 M ax. 9 Typ. 8 M in.
PAGE 15
IR2106(4) (S) 11 V BS UVLO Threshold (-) (V) V BS UVLO Threshold (+) (V) 12 11 M ax. 10 Typ. 9 M in. 8 10 M ax. 9 Typ. 8 M in. 7 6 7 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 Temperature ( C) Temperature ( C) Figure 19. VBS Undervoltage Threshold (+) vs. Temperature Figure 20. VBS Undervoltage Threshold (-) vs. Temperature 500 Output Source Current ( A) 500 Output Source Current ( A) 25 o o 400 300 Typ. 200 M in. 100 400 300 200 Typ. 100 M in.
PAGE 16
IR2106(4) (S) 600 500 Output Sink Current ( A) Output Sink Current ( A) 600 Typ. 400 M in. 300 200 100 0 500 400 300 Typ. 200 M in. 100 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 22A. Output Sink Current vs. Temperature Figure 22B. Output Sink Currentt vs. Supply Voltage V S Offset Supply Voltage (V) 0 -2 Typ. -4 -6 -8 -10 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 23.
PAGE 17
IR2106(4) (S) Case Outlines 01-6014 01-3003 01 (MS-001AB) 8 Lead PDIP D DIM B 5 A FOOTPRINT 8 6 7 6 5 H E 1 2 3 0.25 [.010] 4 A 6.46 [.255] MIN .0532 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BASIC e 3X 1.27 [.050] e1 0.25 [.010] A1 .025 BASIC 0.635 BASIC .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.
PAGE 18
IR2106(4) (S) 14 Lead PDIP 14 Lead SOIC (narrow body) 01-6010 01-3002 03 (MS-001AC) 01-6019 01-3063 00 (MS-012AB) Data and specifications subject to change without notice. 4/3/2003 18 www.irf.