Data Sheet

MPU-6000/MPU-6050 Product Specification
Document Number: PS-MPU-6000A-00
Revision: 3.4
Release Date: 08/19/2013
18 of 52
6.7 I
2
C Timing Characterization
Typical Operating Circuit of Section 7.2, VDD = 2.375V-3.46V, VLOGIC (MPU-6050 only) = 1.8V±5% or
VDD, T
A
= 25°C
Parameters
Conditions
Min
Typical
Max
Units
Notes
I
2
C TIMING
I
2
C FAST-MODE
f
SCL
, SCL Clock Frequency
400
kHz
t
HD.STA
, (Repeated) START Condition Hold
Time
0.6
µs
t
LOW
, SCL Low Period
1.3
µs
t
HIGH
, SCL High Period
0.6
µs
t
SU.STA
, Repeated START Condition Setup
Time
0.6
µs
t
HD.DAT
, SDA Data Hold Time
0
µs
t
SU.DAT
, SDA Data Setup Time
100
ns
t
r
, SDA and SCL Rise Time
C
b
bus cap. from 10 to 400pF
20+0.1C
b
300
ns
t
f
, SDA and SCL Fall Time
C
b
bus cap. from 10 to 400pF
20+0.1C
b
300
ns
t
SU.STO
, STOP Condition Setup Time
0.6
µs
t
BUF
, Bus Free Time Between STOP and
START Condition
1.3
µs
C
b
, Capacitive Load for each Bus Line
< 400
pF
t
VD.DAT
, Data Valid Time
0.9
µs
t
VD.ACK
, Data Valid Acknowledge Time
0.9
µs
Note: Timing Characteristics apply to both Primary and Auxiliary I
2
C Bus
I
2
C Bus Timing Diagram