Instructions
Remove R28 and inject AVCC directly if needed
Design Notes:
Free IO pins: 4.6, 5.0, 5.1, 5.6, 5.7, 7.1, 7.2, 7.3, 7.5, 7.6, 7.7, 8.0, PJ.x (4)
100n
220n
220n
47k
1n
470n
100n
0R
12p
12p
RST
100n
10u
GND
GND
GND
GND
GND
GND
100R
BSL
GND
1k4
1M
GND
CSTCR4M00G15L99
GND
+3V3
+3V3
GND
+3V3
+5V
+3V3
4u7
GND
+3V3
27R
27R
10p
GND
10p
GND
32.768kHz
RESET
LFXTCLK
XT2
Main MSP430F5529 w Power, Clock and USB
1.5
BSL
Speed
Analog VCC
C14
C15
C16
R27
C17
C18
C19
R28
C25
C26
1
2
S3
C29
C30
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
P5.3/XT2OUT
P5.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
RST/NMI/SBWTDIO
P7.7/TB0CLK/MCLK
P7.6/TB0.4
P7.5/TB0.3
P7.4/TB0.2
P5.7/TB0.1
P5.6/TB0.0
P4.7/PM_NONE
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
DVCC2
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
P3.7/TB0OUTH/SVMOUT
P3.6/TB0.6
P4.6/PM_NONE
P3.5/TB0.5
P3.4/UCA...
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
P2.0/TA1.1
P2.1/TA1.2
P2.2/TA2CLK/SMCLK
P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.0/CB8/A12
P7.1/CB9/A13
P7.2/CB10/A14
P7.3/CB11/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF?/VeREF?
AVCC1
P5.4/XIN
P5.5/XOUT
AVSS1
P8.0
P8.1
P8.2
DVCC1
DVSS1
VCORE
U6
MSP430F552x DVSS2
P2.3/TA2.0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R14
1
2
S5
R15
R16
1
2
3
Q4
C27
R31
R32
C23
C24
Q2
P1.4
P2.6
P1.3
P3.2
P1.2
P1.5
P1.7
TARGET_PUR
TEST/SBWTCK
RST/SBWTDIO
P1.0
P1.1
P6.2
P1.6
P6.4
P6.3
P6.1
P6.6
P6.7
P2.0
P4.7
P3.4
P2.5
P3.3
P2.7
P6.0
P2.4
P2.3
P2.1
P2.2
P3.7
P4.0
P6.5
P4.4/UCA1TXD
P4.5/UCA1RXD
P3.6
P4.1
P3.0
P3.1
P3.5
P4.2
P4.3
TARGET_DP
TARGET_DP
TARGET_DM
TARGET_DM HUB_DM1
HUB_DP1
P7.4
P7.0
P8.1
P8.2
+
A
B
C
D
1 2 3 4
A
B
C
D
1 2 3 4
+
Schematics
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6 Schematics
Figure 40. Schematics (1 of 4)
56
MSP430F5529 LaunchPad™ Development Tool (MSP
‑
EXP430F5529LP) SLAU533A–September 2013–Revised January 2014
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