Datasheet
M54HCT138
M74HCT138
February 1993
3 TO 8 LINE DECODER (INVERTING)
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
ORDER CODES :
M54HCT138F1R M74HCT138M1R
M74HCT138B1R M74HCT138C1R
DESCRIPTION
.HIGH SPEED
t
PD
= 16 ns (TYP.) at V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=4µAATT
A
=25°C
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.BALANCEDPROPAGATION DELAYS
t
PLH
=t
PHL
.SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
|=I
OL
.COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS138
The M54/74HC138 is a high speed CMOS 3 TO 8
LINE DECODER fabricated in silicon gate C
2
MOS
technology. It has the same high speed perform-
ance ofLSTTL combinedwithtrue CMOSlowpower
consumption. If the device is enabled, 3 binary se-
lect inputs (A, B and C) determine which one of the
outputs will go low.If enable input G1 is held low or
either G2A or G2B is held high, the decoding func-
tion is inhibited and all the 8 outputs go high. Three
enable inputs are provided toease cascade connec-
tion and application of address decoders for mem-
ory systems. All inputs are equipped with protection
circuits against static discharge and tran- sient ex-
cess voltage.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC
2
MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption.
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