Datasheet

ManualsBrandsUnbranded ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state SOIC 20

M54/74HCT373

M54/74HCT533

October 1993

HCT373 NON INVERTING - HCT533 INVERTING

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT

B1R

(Plastic Package)

ORDER CODES :

M54HCTXXXF1R M74HCTXXXM1R

M74HCTXXXB1R M74HCTXXXC1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTION (top view)

.HIGH SPEED

= 17 ns (TYP.) AT V

=5V

.LOW POWER DISSIPATION

=4µA (MAX.) AT T

=25°C

.COMPATIBLE WITH TTL OUTPUTS

= 2V (MIN.) V

= 0.8 V (MAX.)

.OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

.SYMMETRICAL OUTPUT IMPEDANCE

= I

= 6 mA (MIN.)

.BALANCEDPROPAGATION DELAYS

PLH

PHL

.PIN AND FUNCTION COMPATIBLE

WITH 54/74LS373/533

DESCRIPTION

The M54/74HCT373 and M54HCT533 are high

speed CMOS OCTAL LATCH WITH 3-STATE

OUTPUTS fabricated with in silicon gate C

MOS

technology.

These ICs achive the high speed operation similar

to equivalent LSTTL while maintaning the CMOS

low power dissipation.

These 8 bit D-Type latches are controlled by a latch

enable input (LE) and a output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input precisely or

inversely. When the LE is taken low, the Q outputs

will be latchedprecisely or inversely at the logic level

of D input data. While the OE input is at low level,

the eight outputs will be in a normal logic state (high

or low logic level) and while high level the outpts will

be in a high impedance state. The application

designer has a choise of combination of inverting

and non inverting outputs. The three state output

configuration and the wide choise of outline make

bus organized system simple.

These integrated circuits have input and output

characteristics that are fully compatible with 54/74

LSTTL logic families. M54/74HCT devices are

designed to directly interface HSC

MOS systems

with TTL and NMOS components. They are also

plug in replacements for LSTTL devices giving a

reduction of power consumption. All inputs are

equipped with protection circuits against discharge

and transient excess voltage.

HCT373 HCT533 HCT373 HCT533

1/13

Summary of content (13 pages)

PAGE 1
M54/74HCT373 M54/74HCT533 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT373 NON INVERTING - HCT533 INVERTING . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8 V (MAX.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.
PAGE 2
M54/M74HCT373/533 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION (HCT373) PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 11 LE 10 20 GND V CC NAME AND FUNCTION PIN DESCRIPTION (HCT533) PIN No SYMBOL 1 OE 3 State outputs 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3 State outputs Data Inputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 Data Inputs 3 State output Enable Input (Active LOW) NAME AND FUNCTION 3 State output Enable Input (Active LOW) Lat
PAGE 3
M54/M74HCT373/533 TRUTH TABLE INPUTS OUTPUTS OE H LE X D X Q (HCT373) Z Q (HCT533) Z L L L L H H X L H NO CHANGE * L H NO CHANGE * H L X: DON’T CARE Z: HIGH IMPEDANCE *: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.
PAGE 4
M54/M74HCT373/533 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC VI Supply Voltage DC Input Voltage -0.5 to +7 -0.5 to VCC + 0.5 V V VO DC Output Voltage -0.5 to VCC + 0.
PAGE 5
M54/M74HCT373/533 DC SPECIFICATIONS Test Conditions Symbol Parameter VCC (V) VIH High Level Input Voltage 4.5 to 5.5 V IL Low Level Input Voltage 4.5 to 5.5 V OH High Level Output Voltage VOL II IOZ ICC ∆ICC Low Level Output Voltage Input Leakage Current 3 State Output Off State Current Quiescent Supply Current Additional worst case supply current Value TA = 25 oC 54HC and 74HC Min. Typ. Max. 2.0 -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 2.0 0.8 4.
PAGE 6
M54/M74HCT373/533 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 6 ns) Test Conditions o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 15 18 Symbol Parameter VCC (V) CL (pF) tTLH tTHL Output Transition Time 4.5 50 TA = 25 C 54HC and 74HC Min. Typ. Max. 7 12 tPLH tPHL Propagation Delay Time (LE - Q) 4.5 4.5 50 150 20 24 30 37 38 46 45 56 ns ns tPLH tPHL Propagation Delay Time (D - Q) 4.5 50 19 30 38 45 ns 4.
PAGE 7
M54/M74HCT373/533 SWITCHING CHARACTERISTICS TEST WAVEFORM tPLH, tPHL, ts, th, tw fMAX tPLZ, tPZL The 1KΩ load resistors should be connected between outputs and VCC line and the 50pF load capacitors should be connected between outputsand GND line. All inputs except OE input should be connected to VCC line or GND line such that outputs will be in low logic level while OE input is held low. tPHZ, tPZH The 1KΩ load resistors and the 50pF load capacitors should be connected between each output and GND line.
PAGE 8
M54/M74HCT373/533 TEST CIRCUIT ICC (Opr.
PAGE 9
M54/M74HCT373/533 Plastic DIP20 (0.25) MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.
PAGE 10
M54/M74HCT373/533 Ceramic DIP20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 25 0.984 B 7.8 0.307 D E 3.3 0.5 e3 0.130 1.78 0.020 22.86 0.070 0.900 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 I 1.27 1.52 0.050 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N1 P Q 4° (min.), 15° (max.) 7.9 8.13 5.71 0.311 0.320 0.
PAGE 11
M54/M74HCT373/533 SO20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8° (max.
PAGE 12
M54/M74HCT373/533 PLCC20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 9.78 10.03 0.385 0.395 B 8.89 9.04 0.350 0.356 D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022 E 7.37 8.38 0.290 0.330 e 1.27 0.050 e3 5.08 0.200 F 0.38 0.015 G 0.101 0.004 M 1.27 0.050 M1 1.14 0.
PAGE 13
M54/M74HCT373/533 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice.